Alvin Lee

Optimization of temporary bonding through high-resolution metrologies to realize ultrathin wafer handling

Interest has intensified in temporary wafer bonding technology for thin wafer handling to realize 3D system integration. Several challenges such as thermal stability, process compatibility, and chemical resistance for temporary adhesives have been addressed in numerous publications. However, the correlation of thickness variation among carrier, temporary adhesive, temporary bonding, and final thinning thickness is rarely discussed because of limitations in metrology. The work described here utilized a WaferBOND® advanced bonding material and ZoneBOND® [1] technology from Brewer Science, Inc., as well as the Tropel® FlatMaster® MSP-300 and semiconductor glass wafers from Corning Incorporated to evaluate the influence of each layer and suitable metrology to enhance overall performance.

Ultrathin glass wafer lamination and laser debonding to enable glass interposer fabrication

Interposer fabrication processes are applied in three-dimensional (3-D) integrated circuit (IC) integration to shorten the interconnection among different stacked chips and substrates. Because Si is a common material in semiconductor technology, Si interposers have been widely studied in many research activities. Compared with a Si wafer, glass substrates have the advantages of high resistivity, low dielectric constant, low insertion loss, adjustable coefficient of thermal expansion (CTE), and the possibility to use panel-size substrates as well as thin glass substrates (100 μm) to avoid the costly thinning process for realization of low-cost 2.5-D ICs. Thus, glass interposer fabrication is studied thoroughly in this paper. Thin glass wafers have reduced mechanical stiffness. Therefore, handling and shipping thin glass wafers (≤100 μm) throughout the semiconductor fabrication and packaging assembly processes are critical. Temporary wafer bonding technology is used in this study to bond a thin glass wafer to a carrier to improve the rigidity. Vacuum lamination technology is used in this study as a bonding process to enhance the costeffectiveness. After processing, the carrier is removed by laser debonding. The thin glass wafer with structures on both sides does not need to undergo a glass thinning process and saves a lot of cost compared to the traditional glass or Si interposer processes. Thin 300-mm glass wafers 100 μm thick are evaluated as: (a) blank thin glass wafers and (b) thin glass wafers with through-glass vias (TGVs) 30 μm in diameter. A UV laser with a wavelength of 308 nm, which has the benefit of less impact to the device, was adopted to laser debonding. This method also has several benefits such as high throughput, low temperature, zero-force debonding, and possible selective laser debonding. Adhesive and release layers are key enabling materials for thin glass handling. In addition, the use of a laminator for temporary bonding and laser debonding are included in this study. Based on the excellent fabrication, the thin glass interposer has great potential to be applied in 2.5-D integration applications.

Advanced processes and materials for temporary wafer bonding

Advances in semiconductor technology are still being made in traditional lithography techniques, however, the industry is beginning to look into alternative ways to reduce size and form factor while increasing performance at the same time. One such pathway is to stack various functional chips vertically. To do this, the base substrate must be very thin to allow for electrical connections, termed through-silicon-vias, to pass through. Once the substrate is thinned, it is very fragile and must be supported, either in a built up package or by being attached to a temporary carrier or handle wafer. The former is a permanent chip-to-wafer bonding, while the latter is a temporary wafer bonding. Both methods play roles in enabling chip stacking for the creation of three-dimensional integrated circuits as well as many other advanced micro devices such as MEMS. The purpose of this research was to develop a specialized method of temporary wafer bonding to enable the transfer of fragile device wafers from one carrier to another to allow processing on both sides of the device wafer in multiple sequences. The work utilized ZoneBOND™ technology from Brewer Science, Inc. to create multiple zones on carrier substrates using advanced materials with different solubilities. In this process, a simulated device wafer was temporarily bonded to a first carrier using one adhesive. Then a second carrier was bonded to the opposite side of the device wafer using a different adhesive. Then the stack was exposed to a solvent that selectively softened the adhesive on the outer zone of the first carrier. This carrier was then removed, thus transferring the device wafer from the first to the second carrier.

Laminating thin glass onto glass carrier to eliminate grinding and bonding process for glass interposer

Interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and the substrate [1]. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE as well as the ability to provide a low cost solution [2]. In this investigation, another cost reduction concept of through glass via (TGV) wafer processing is being studied. By leveraging current semiconductor equipment and know-how, we bond TGV wafers onto glass carriers as shown in Figure 1, the TGV wafer thickness is directly 100um and center diameter (CD) of through glass via is 30 μm. This approach provides a method to temporarily bond these TGV wafers to glass carriers enabling handling through processes such as via fill and surface metallization. The ability to form glass at the target 100 um thickness and provide through holes and thus avoid backgrinding processes provides substantial opportunity to save costs and avoid yield loss. The TGV interposer wafer is bonded with a glass carrier by a polymeric bonding material. The bonding material must be compatible with surface materials as well as good step coverage to void-free bonding [3]. Most importantly, the bonding material shall remain stable and good resistance in harsh thermal and chemical environments to protect interposer at all time [4]. The thermal stability and characteristics of the bonding material used in this study as shown in Figure 2, is important to maintain low warp. Finally, the treated glass carrier is released from the bonding material by a laser de-bond method. The laser debond method is known to have several benefits such as (a) high throughput: possible to de-bond one pair within 30s (b). low temperature: UV range wavelength does not generate heat in the de-bonding process (c). zero force de-bon ding: after laser scanning, the carrier can be lifted off directly (d). process efficiency: laser release layer is a spin-on material, so only a spin bowl is required. Here we use 308 nm laser and this wavelength also has the benefit with less impact to the device.

Optimization for temporary bonding process in PECVD passivated micro-bumping technology

One of the key processes of 3-D IC technology is the implementation of a temporary bonding solution that gives the ability to handle and process thinned Si wafers. Figure 1 depicts thin composite wafers going through a typical process from bare wafer through micro-bumping. The thin composite wafers are processed (Figure 1, steps 7 to 11) sequentially including PECVD, sputtering, patterning, electro-plating, photoresist (PR) stripping, and reflow. In general, the dielectric quality and surface conformity of most plasma-deposited insulators increases significantly as the temperature increases from 200°C to 300°C [1]. Hence, the process of PECVD includes higher temperatures (>200°C) and longer times (~10 minutes) compared with other processes. Chipping or cracking may occur at the wafer edge after the PECVD process [2]. Some dishing as large as a chip size (5 mm × 5 mm) can also randomly occur at the wafer surface, as shown in Figure 2 [3], presumably caused by outgassing from the adhesive layer [2]. Therefore, it is critical to account for PECVD when designing the temporary bonding process. Due to the long high-temperature thermal treatment in the PECVD process, bonding materials play a critical role. The work described here utilized WaferBOND® advanced bonding material and ZoneBOND® technology from Brewer Science, Inc. The impact of the bonding materials with different thermal stability, provided by Brewer Science, are studied in this paper. Glass total thickness variation (TTV) and flatness impacts the overall performance of temporary bonding technology [4]. Also, deposition of certain coatings can impact the flatness (warp/bow) of high-aspect-ratio wafers. Finally, mismatch of the coefficient of thermal expansion (CTE) of the various components of a bonded stack will also affect the overall flatness as a function of process temperature. For these reasons, a study was conducted to better understand the impact of warpage and CTE of the glass carrier wafer, as well as the impact of coating-induced warpage on the performance of a temporary bonding/debonding process. An L9 Taguchi experiment method was used with split condition design to understand the parameters of this study. A PECVD process at 250°C with different thickness was performed in the Electronics and Optoelectronics Lab (EOL) within the Industrial Technology Research Institute (ITRI) to coat the Si wafers. Corning® Semiconductor Glass Wafers and simulated silicon (Si) wafers were carefully treated and coated with ZoneBOND® advanced materials and WaferBOND® bonding material. After bonding, simulated processes (e.g., silicon nitride coating) were performed. At each step, Cornings FlatMaster® MSP 300 tool was used to collect thickness variation and warpage data to evaluate the performance of the temporary bonding process.

Process Development and Material Characteristics of TSV-Less Interconnection Technology for FOWLP

Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.

A low-temperature temporary lamination and laser debonding technology to enable cost-effective fabrication of a through-glass-via (TGV) interposer on a panel substrate

This paper describes a handling process for a thin glass panel, 200 mm × 200 mm × 130 (im, through double-side redistribution layer (RDL) formation to enable cost-effective fabrication of through-glass-via (TGV) interposers. The integration scheme includes lamination of a low-temperature bonding material utilizing a lamination process temperature of less than 100°C to bond a thin (130-μm) glass panel onto a carrier glass panel 700 μm thick. The carrier glass panel is treated with a 150-nm laser release layer prior to lamination of the bonding film and subsequently the thin glass panel. Next, the RDL is formed, and the front side of the thin glass panel undergoes aluminum physical vapor deposition (PVD) and polymeric dielectric material deposition. Then a second carrier glass panel, treated with the laser release material and laminated with bonding film, is bonded on the front side of the thin glass panel. An excimer laser with an x-y scanning stage is rastered across the first carrier to ablate the laser release layer for separation of first carrier. Following laser separation, a solvent cleaning step is performed to remove bonding material from the backside of the thin glass panel. The process of applying metal PVD, lithography, and dielectric material is repeated on the backside of the thin glass panel. Finally, the thin glass panel is mounted to tape, and the second carrier glass panel is released using laser ablation to reveal the front side of the thin glass for solvent cleaning and final inspection. The integration of the dry bonding film, thin glass panel lamination, and selective laser debonding technology in this study will pave the way for realization of panel-level packaging in the near future.

Metrologies for characterization of flatness and thickness uniformity in temporarily bonded wafer stacks

In the past few decades, the semiconductor industry has grown very quickly and the technology has advanced as predicted by Moores law. In order to improve the cost effectiveness of semiconductor processes, the device size has been reduced, but the wafer diameter continues to increase. Furthermore, in order to overcome the barrier of Moores law, Three-Dimensional Stacked Integrated Circuits (3DS-IC) integration technology attracts more and more interests in the semiconductor industry. One of the key processes of 3DS-IC technology is the implementation of temporary bonding solution which gives the ability to handle and process thinned Si wafers. Flatness and thickness uniformity of a thin Si wafer is critical for product reliability and yield. As a result, not only total thickness variation (TTV) of the thin Si wafer but also TTV/flatness of the wafer stack matters. As the temporary bonding process evolves, glass carriers have become a promising solution because of flexibility and excellent attributes given by adjustability of composition. Substantial benefits are also realized from Cornings optimized fusion forming process. It is, therefore, extremely important that the flatness and TTV of the carrier wafer are well characterized to ensure expected performance. Flatness and thickness characterization of a temporary bonded stack is challenging due to different aspects. Firstly, as the diameter increases, stiffness of the wafer decreases. Significant sag is observed when the wafer is measured on a conventional points mount fixture. The sag could be so large that removing gravity is non-trivial. Secondly, the absorption spectrums of glass and Si could be quite different. Non-contact optical metrology has to work for both materials. Thirdly, precise metrology which can provide high resolution (lateral and thickness) of the thickness uniformity map in order to fulfill requirements of downstream processes is needed. Corning® Tropel® MSP300® is a novel distance measuring interferometer based on a frequency stepping laser that is well suited to characterize flatness and TTV of glass. This metrology tool implements a novel mounting solution which prevents gravity induced wafer sag. It also realizes a much higher lateral resolution compared to the commercial metrology tools which only scan wafers along distinct slices and interpolate data in regions between these slices.For comparison studies of different mounting strategies and scan techniques, we characterize the wafer stack not only by MSP300, but also by a scanning system, which integrates translational stages and a low coherence interferometer (LCI) operating at infrared wavelength. Commercial software is used to generate data in the region between distinct scan slices. The wafer stack is composed of glass carriers and Si wafers implemented by ZoneBOND® from Brewer Science. The thinning process is also carried out on the Si wafers after wafer bonding. Variation of attributes of glass carriers are utilized for correlation study. The impact of various attributes of the glass wafer and bonding process, as well as the importance to suitably characterize the carrier wafer (data density, resolution, and mounting technique) will be demonstrated.