Wen-Wei Shen

Investigation of the process for glass interposer

Through glass via (TGV) interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and substrate. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed and there are many challenges for processing. For process, the major differences between Glass and Si interposer are method for via formation and isolation. The test vehicle for Glass interposer is successfully processed. Glass material is composed with SiOx, it is good isolation for electrical current. The polymer-based PBO is used for passivation. For structure of glass interposer, there is one RDL on the front-side and backside, respectively. The other structure is 2 RDL on the front-side and one RDL one the backside. The CD of through glass via is 30 μm, it is formed by Corning Co. Cu overburden and Ti barrier are removed by wet etching process. For top RDL (line-width = 20μm), Cu plating process with seed layer (Ti/Cu) wet-etching process is applied. The PBO material is used for passivation, the process temperature is blow 200°C. Top UBM (15μm in diameter; 4μm/5μm-thick Cu/Sn) is formed with a top passivation opening (15μm). The structure is analyzed and demonstrated by SEM analysis. All the results indicate that the glass interposer with polymer passivation can be preceded and the cost for process is cheaper than Si interposer.

Ultrathin glass wafer lamination and laser debonding to enable glass interposer fabrication

Interposer fabrication processes are applied in three-dimensional (3-D) integrated circuit (IC) integration to shorten the interconnection among different stacked chips and substrates. Because Si is a common material in semiconductor technology, Si interposers have been widely studied in many research activities. Compared with a Si wafer, glass substrates have the advantages of high resistivity, low dielectric constant, low insertion loss, adjustable coefficient of thermal expansion (CTE), and the possibility to use panel-size substrates as well as thin glass substrates (100 μm) to avoid the costly thinning process for realization of low-cost 2.5-D ICs. Thus, glass interposer fabrication is studied thoroughly in this paper. Thin glass wafers have reduced mechanical stiffness. Therefore, handling and shipping thin glass wafers (≤100 μm) throughout the semiconductor fabrication and packaging assembly processes are critical. Temporary wafer bonding technology is used in this study to bond a thin glass wafer to a carrier to improve the rigidity. Vacuum lamination technology is used in this study as a bonding process to enhance the costeffectiveness. After processing, the carrier is removed by laser debonding. The thin glass wafer with structures on both sides does not need to undergo a glass thinning process and saves a lot of cost compared to the traditional glass or Si interposer processes. Thin 300-mm glass wafers 100 μm thick are evaluated as: (a) blank thin glass wafers and (b) thin glass wafers with through-glass vias (TGVs) 30 μm in diameter. A UV laser with a wavelength of 308 nm, which has the benefit of less impact to the device, was adopted to laser debonding. This method also has several benefits such as high throughput, low temperature, zero-force debonding, and possible selective laser debonding. Adhesive and release layers are key enabling materials for thin glass handling. In addition, the use of a laminator for temporary bonding and laser debonding are included in this study. Based on the excellent fabrication, the thin glass interposer has great potential to be applied in 2.5-D integration applications.

Laminating thin glass onto glass carrier to eliminate grinding and bonding process for glass interposer

Interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and the substrate [1]. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE as well as the ability to provide a low cost solution [2]. In this investigation, another cost reduction concept of through glass via (TGV) wafer processing is being studied. By leveraging current semiconductor equipment and know-how, we bond TGV wafers onto glass carriers as shown in Figure 1, the TGV wafer thickness is directly 100um and center diameter (CD) of through glass via is 30 μm. This approach provides a method to temporarily bond these TGV wafers to glass carriers enabling handling through processes such as via fill and surface metallization. The ability to form glass at the target 100 um thickness and provide through holes and thus avoid backgrinding processes provides substantial opportunity to save costs and avoid yield loss. The TGV interposer wafer is bonded with a glass carrier by a polymeric bonding material. The bonding material must be compatible with surface materials as well as good step coverage to void-free bonding [3]. Most importantly, the bonding material shall remain stable and good resistance in harsh thermal and chemical environments to protect interposer at all time [4]. The thermal stability and characteristics of the bonding material used in this study as shown in Figure 2, is important to maintain low warp. Finally, the treated glass carrier is released from the bonding material by a laser de-bond method. The laser debond method is known to have several benefits such as (a) high throughput: possible to de-bond one pair within 30s (b). low temperature: UV range wavelength does not generate heat in the de-bonding process (c). zero force de-bon ding: after laser scanning, the carrier can be lifted off directly (d). process efficiency: laser release layer is a spin-on material, so only a spin bowl is required. Here we use 308 nm laser and this wavelength also has the benefit with less impact to the device.

An RDL-First Fan-out Wafer Level Package for Heterogeneous Integration Applications

Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.

Process Development and Material Characteristics of TSV-Less Interconnection Technology for FOWLP

Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.

Reliability evaluation of glass interposer module

In this paper, we investigate reliability testing for a glass interposer. The test vehicle is an assembled glass interposer with a chip, a BT substrate. The structure of a glass interposer with two redistribution layers (RDLs) on the front-side and one RDL on the back-side has been evaluated and developed. Key technologies, including via fabrication, front-side RDL formation, microbumping, temporary bonding, glass thinning, and back-side RDL formation, have been developed and integrated for high performance. The BT substrate design and PCB for electrical characterization of reliability tests are reported in this paper. The results indicate that this glass interposer can be integrated. The data show the feasibility of this glass interposer for electronics applications.

Reliability test for integrated Glass interposer

In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass thinning and backside RDL formation, were developed and integrated to perform well. The BT substrate design and PCB for electrical characterization of reliability tests are included as well. The results indicate that the device with the glass interposer can be integrated and there is also data showing the feasibility of the glass interposer for electronics applications.

A low-temperature temporary lamination and laser debonding technology to enable cost-effective fabrication of a through-glass-via (TGV) interposer on a panel substrate

This paper describes a handling process for a thin glass panel, 200 mm × 200 mm × 130 (im, through double-side redistribution layer (RDL) formation to enable cost-effective fabrication of through-glass-via (TGV) interposers. The integration scheme includes lamination of a low-temperature bonding material utilizing a lamination process temperature of less than 100°C to bond a thin (130-μm) glass panel onto a carrier glass panel 700 μm thick. The carrier glass panel is treated with a 150-nm laser release layer prior to lamination of the bonding film and subsequently the thin glass panel. Next, the RDL is formed, and the front side of the thin glass panel undergoes aluminum physical vapor deposition (PVD) and polymeric dielectric material deposition. Then a second carrier glass panel, treated with the laser release material and laminated with bonding film, is bonded on the front side of the thin glass panel. An excimer laser with an x-y scanning stage is rastered across the first carrier to ablate the laser release layer for separation of first carrier. Following laser separation, a solvent cleaning step is performed to remove bonding material from the backside of the thin glass panel. The process of applying metal PVD, lithography, and dielectric material is repeated on the backside of the thin glass panel. Finally, the thin glass panel is mounted to tape, and the second carrier glass panel is released using laser ablation to reveal the front side of the thin glass for solvent cleaning and final inspection. The integration of the dry bonding film, thin glass panel lamination, and selective laser debonding technology in this study will pave the way for realization of panel-level packaging in the near future.