Anda Mocuta

Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1-μm and 70-nm gate lengths. Hole mobility at 1-μm gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.

Relaxation of time-dependent NBTI variability and separation from RTN

NBTI and RTN time-dependent variability is described from a defect-centric perspective. It is shown that NBTI induced threshold voltage shift (ΔVTH) distribution is governed by a compound Exponential-Poisson process. Using the memoryless properties of Poisson statistics, it is shown that not only the stressed but also the relaxed fraction follows the Exponential-Poisson distribution. Moreover, the relaxed fraction is shown to be independent from the final remaining ΔVTH. Using the same statistical model, the separation of RTN induced ΔVTH from NBTI is shown which allows a more accurate estimation of the characteristic distribution parameters. Finally, it is shown that RTN is a wide-sense stationary noise source of which the autocorrelation can be extracted from analysis of NBTI relaxation traces.

Low track height standard cell design in iN7 using scaling boosters

In this paper, standard cell design for iN7 CMOS platform technology targeting the tightest contacted poly pitch (CPP) of 42 nm and a metal pitch of 32 nm in the FinFET technology is presented. Three standard cell architectures for iN7, a 7.5-Track library, 6.5-Track library, and 6-Track library have been designed. Scaling boosters are introduced for the libraries progressively: first an extra MOL layer to enable an efficient layout of the three libraries starting with 7.5-Track library; second, fully self aligned gate contact is introduced for 6.5 and 6-Track library and third, 6-Track cell design includes a buried rail track for supply. The 6-Track cells are on average 5% and 45% smaller than the 6.5 and 7.5-Track cells, respectively.

Band-to-band tunneling off-state leakage in Ge fins and nanowires: Effect of quantum confinement

This simulation work studies whether band-to-band-tunneling leakage in short-channel germanium FinFETs and nanowires can be mitigated by the band gap widening resulting from quantum confinement. Through a combination of drift-diffusion and coupled Poisson-Schrödinger simulations, two possible solutions are investigated: can the BTBT rate be lowered sufficiently? Secondly, can the tunnel path be cut off by band gap widening? Our results indicate that by exploiting the band gap widening in narrow devices, gate-induced drain leakage due to band-to-band tunneling in Ge FinFETs and nanowires can meet the high-performance and low operating power off-state leakage specifications of CMOS technology. However, the low standby power off-state target seems out of reach.

FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below

This simulation work studies whether optimal wafer and channel orientations exist that maximize the mobility of 10 nm-node strained-silicon FinFETs. For NFinFETs, strain-relaxed buffers or source/drain stressors yield the highest mobilities on rotated-notch wafers. For PFinFETs, industry-standard directions give the highest mobilities when using Si1-yCy strain-relaxed buffers as a stress booster. Using {110} substrates leads to strained mobilities that are in between what can be obtained by industry-standard and rotated-notch directions.

Extracting the effective bandgap of heterojunctions using Esaki diode I-V measurements

The effective bandgap is a crucial design parameter of heterojunction tunneling field-effect transistors. In this letter, we demonstrate a method to measure the effective bandgap directly from the band-to-band tunneling current of a heterojunction Esaki diode, of which we only require knowledge of the electrostatic potential profile. The method is based on a characteristic exponentially increasing current with forward bias, caused by sharp energy filtering at cryogenic temperature. We apply this method experimentally to a n+In0.53Ga0.47As/pGaAs0.5Sb0.5 Esaki diode and define requirements to apply it to other heterojunctions.

Novel method to determine the band offset in hetero staggered bandgap TFET using Esaki diodes

Summary form only given. In heterojunction Tunneling Field-Effect Transistors (TFET), the effective tunneling bandgap (Eg,eff) has a strong impact on the on-current (Ion) and the subthreshold swing (SS) (figure 1). There is however significant uncertainty on Eg,eff for the staggered heterojunction In0.53Ga0.47As/GaAs0.50Sb0.50 (InGaAs/GaAsSb), with values in literature ranging from 0.5 eV to 0.27 eV [3-6]. An additional problem is that Eg,eff is usually measured optically on lowly doped heterojunctions [7-8]. These values may be far off for use in TFETs where there is bandgap narrowing due to heavy doping (doping-BGN) in the source and pocket regions. The impact of doping-BGN on Band-To-Band Tunneling (BTBT) is currently not well understood, contributing to the difficulty in making quantitative hetero-TFET predictions.

Track height reduction for standard-cell in below 5nm node: how low can you go?

The targeted 5nm and below technology node at IMEC has been defined by poly pitch 42nm and metal pitch 21nm. Compared to the previous node the CPP [1] remains the same and only the metal pitch is scaled down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore’s law. Here we present some of the options for the standard cell design that may enable this advance technology node and will require scaling boosters as Design-Technology co-optimization (DTCO).

Defect-based compact modeling for RTN and BTI variability

This paper describes a defect-centric based compact modeling methodology for time-dependent threshold voltage variability (VTH), induced by Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN). A Verilog-A based model wrapper is used to implement a threshold voltage shift by adding a variable voltage source at the gate of the core device model. This compact model allows to incorporate all BTI and RTN related electrostatics and kinetics in standard EDA-tools as a ‘black box’ without any custom simulation flow. It can therefore be used in either a manual configuration for academic purposes or be integrated as is into industry standard EDA tools and simulation flows.

Nonparabolicity and confinement effects of IIIV materials in novel transistors

Employing a 8 band k.p solver, the self-consistent band structure of the rectangular IIIV nanowires (NW) has been calculated. It is shown that the strong confinement combined with the band nonparabolicity will considerably change the effective masses and the band gap. The mass tensor elements get heavier than the bulk values and improve the density of state (DOS) and centroid capacitance accordingly, while in return the mobility will be degraded. The band widening has also been calculated for different width and height combinations. It is shown that oxide thickness scaling cannot compensate the poor DOS of IIIV, where the silicon device exhibits a continuous performance boost by thinning the oxide layer. Possible improvements of DOS through the width and the mole fraction modulation have been investigated.