Andrea Fornasari

Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators

We propose a digital background adaptive calibration technique for correcting offset and gain mismatches in time-interleaved multipath analog-digital (A/D) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed technique allows us to cancel the spurious tones introduced by offset and gain mismatches among the paths only by processing the digital output, without interfering with the operation of the modulator. This solution is also effective for any other time-interleaved A/D converter topology. Simulation results on a high-performance four-path bandpass /spl Sigma//spl Delta/ modulator, operating on a 5-MHz band at a clock frequency of 320 MHz, demonstrate the effectiveness of the proposed calibration technique, which allows us to achieve significant improvements of the signal-to-noise ratio and the spurious-free dynamic range in the presence of mismatches.

A Micropower Chopper—CDS Operational Amplifier

A low-power spur-free precision amplifier, which uses input chopping and correlated double sampling for demodulation, is presented. This circuit employs an AC coupling between the first and the second stage that removes the first stage offset without causing ripple. The input rail-to-rail circuit, fabricated in a mixed 0.18-0.5 μm CMOS technology, operates with supply ranging from 1.8 V to 5 V. The circuit achieves a simulated 168-dB DC gain with an overall current consumption of 14.4 μA. The measured offset voltage over the available samples results in a distribution with 2-μV standard deviation. The obtained input noise density at low-frequency equal to 37 nV/√Hz gives a 5.5 noise efficiency factor.

A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator

This paper describes a 0.35-/spl mu/m CMOS fourth-order bandpass analog-digital sigma-delta (/spl Sigma//spl Delta/) modulator for wide-band base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The /spl Sigma//spl Delta/ modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 mm/sup 2/ of silicon area.

Improved modeling of sigma-delta modulator non-idealities in Simulink

The goal of this paper is to present an extension of previously presented behavioral models, implemented in the Matlab/Simulink/spl trade/ environment. This toolbox allows us to simulate at behavioral level most of the switched-capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulator non-idealities, such as sampling jitter, kT/C noise and operational amplifier limitations (finite bandwidth, finite DC gain, slow rate and saturation). Although very effective in simulating wide-band, medium-resolution /spl Sigma//spl Delta/ converters the lack of a model for flicker noise and multi-bit quantizers makes this toolbox less attractive for simulating narrow band high resolution converters. The proposed extension not only fixes this limitation, but introduces a predictive model of the effect of capacitor mismatch in the internal multi-bit D/A converter.

Use of dynamic element matching in a multi-path sigma-delta modulator

This paper describes the use of dynamic element matching in a multi-bit, multi-path sigma-delta modulators. The technique achieves noise shaping and enables the use of elements with 0.5% mismatch. Simulation results at the behavioral and gate level shows the possibility to achieve an SNR as large as 85 dB and SFDR of 90 dB with a 320 MHz equivalent clock frequency.

A micropower chopper-correlated double-sampling amplifier with 2µV standard deviation offset and 37nV/√Hz input noise density

A key limit of the chopper stabilized technique is that the low-frequency noise after being shifted up to the chopping frequency is only partially removed by filtering. The auto-zero method does not suffer this limit, but the aliasing of the broadband input noise spectrum imposes the use of large sampling capacitances that, in turn, increase the bias current. The chopper method is the optimal approach for micro-power applications.

A 1.0 mW, 71 dB SNDR, −1.8 dB FS input swing, fourth-order ΣΔ interface circuit for MEMS microphones

In this paper a large input swing integrated interface circuit for MEMS microphones is presented. It consists of an high impedance input buffer followed by a multi-bit (12-levels) analog second order ΣΔ modulator and a fully-digital single-bit fourth-order ΣΔ modulator. The circuit, supplied with 3.3V, exhibits a current consumption of 215 µA for the analog part and 95 µA for the digital part. The measured signal-to-noise and distortion ratio (SNDR) is 71 dB, with an input signal amplitude as large as −1.8 dB with respect to full-scale, obtained thanks to the use of a feed-forward technique, which relaxes the voltage swing requirements of the operational amplifiers. The test chip fabricated in a 0.35 µm CMOS occupies an area of 3 mm2 including pads.

Low-power ripple-free chopper amplifier with correlated double sampling de-chopping

This paper presents a new solution to obtain a spurs-free high precision amplifier. The method involves input chopping and correlated double sampling signal de-chopping. The offset is removed by using DC coupling. The proposed method, verified with transistor level simulations, is applied to a rail-to-rail input amplifier with 187 dB DC gain and 13.7 µA current consumption.

On-line calibration and digital correction of multi-bit sigma-delta modulators

This paper presents a new method for the on-line calibration of the elements of the digital-to-analog converter (DAC) used in the feedback loop of multi-bit sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed method, with an extremely limited amount of additional circuitry, allows the mismatches among the elements of the DAC to be accurately measured and corrected in the digital domain, thus improving the linearity performance of the modulator. A switched-capacitor (SC) 4-bit /spl Sigma//spl Delta/ modulator has been implemented to validate the proposed solution. The experimental results confirm that this method allows us to achieve an improvement in the spurious-free dynamic range as large as 26 dB.

A particle detector fully-programmable interface circuit for satellite applications

In this paper we propose a fully integrated analog acquisition channel for the new generation of /spl gamma/-ray detectors. The channel does not include a charge sensitive amplifier (CSA), because the CSA itself is mounted on the detector. This approach relaxes significantly the noise specifications of the channel, but requires the programmability of the most important parameters of the circuit (gain, shaping time, threshold, polarity, pole-zero cancellation) to allow the same analog channel to be connected to many types of detector/CSA pairs. The channel includes also a 10 bit A/D converter and hence provides digital output. The programming of the parameters is performed digitally. The chip, fabricated using a CMOS 0.8 /spl mu/m technology, consumes 30 mW from a 5 V power supply.