Andreas Scholze

Analysis of Gate-Induced Drain Leakage Mechanisms in Silicon-Germanium Channel pFET

Silicon-germanium is an alternative channel material for pMOS FETs at 32-nm node and beyond because of lower threshold voltage and higher channel mobility in high-k metal gate technology. However, gate-induced drain leakage (GIDL) is a major concern at low power technology nodes because of band-to-band and trap-assisted tunneling (TAT) due to reduced bandgap. Here, we have studied the GIDL dependence on temperature as well as drain and substrate bias. Experimental results and Technology computer-aided design (TCAD) simulations suggest that the mechanism responsible for GIDL during off state is mostly phonon-assisted band-to-band tunneling (BTBT) in the top SiGe layer near the drain surface and is further contributed by BTBT at the drain sidewall junction. Other GIDL mechanisms such as TAT at the extension/sidewall dominate for other drain, gate, and substrate bias voltages.

Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs

The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM). The calibration method for the stress-induced channel mobility and the external resistance is proposed using Ron-Lgate measurements of 32nm-node devices with different gate-pitches. The significant performance degradation due to simple gate-pitch scaling is predicted for 20nm-node technology with sub-100nm gate-pitch.

Investigation of Fixed Oxide Charge and Fin Profile Effects on Bulk FinFET Device Characteristics

The effect of positive fixed oxide charge (Qf) on the electrical characteristics of bulk FinFET devices is investigated and newly addressed as a Fin scaling detractor. The aggressively scaled Fin width leads to abnormal subthreshold slope (SS) degradation in nMOS devices even with a long channel length, while pMOS is free of such degradation. This observation is reproduced and analyzed by a well-calibrated TCAD simulation deck with Qf introduced. A new Fin profile suppressing the Qf effect is proposed, and the benefits of the new profile are predicted in terms of variability reduction and mobility improvement, as well as Qf immunity.

New implantation tables for B, BF 2 , P, As, In and Sb

After implantation, the distribution of ions can be described by analytical functions with parameters depending on implantation conditions. In this work, a calibrated Monte Carlo simulator was used to calculate tables for the implantation of B, BF2, P, As, In and Sb. Starting from systematic Monte Carlo data we extracted the parameters of two Pearson functions for dopant profiles in crystalline silicon and single Pearson functions for profiles in SiO2, Si3N4 and poly-silicon. The new tables cover more dopant species and implantation conditions than existing implantation tables and provide excellent agreement with 90 SIMS profiles. In a 2D nMOS test case, the implantation simulation with the new tables provides the same accuracy as Monte Carlo simulations.

Exploring MOL design options for a 20nm CMOS technology using TCAD

A mixed-mode simulation framework is presented to study the AC performance of a 20nm bulk CMOS technology with respect to various options for contact design at the middle-of-line design level. These simulations combine the predictive capabilities of a calibrated two-dimensional TCAD model for a MOSFET with three-dimensional simulations for the layout dependent parasitic capacitances to extract the characteristic parameters of a multi-stage ring-oscillator circuit, such as the ring delay, and the effective switching capacitance. Significant performance degradation is predicted comparing the simulation results for a conventional contact design versus a typical 20nm design considering raised source-drain and a contact bar.