Andres Bryant

Silicon CMOS devices beyond scaling

To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/µm for the 250-nm node to hundreds of nA/µm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit.

Ultralow-voltage, minimum-energy CMOS

Energy efficiency has become a ubiquitous design requirement for digital circuits. Aggressive supply-voltage scaling has emerged as the most effective way to reduce energy use. In this work, we review circuit behavior at low voltages, specifically in the subthreshold (Vdd < Vth) regime, and suggest new strategies for energy-efficient design. We begin with a study at the device level, and we show that extreme sensitivity to the supply and threshold voltages complicates subthreshold design. The effects of this sensitivity can be minimized through simple device modifications and new device geometries. At the circuit level, we review the energy characteristics of subthreshold logic and SRAM circuits, and demonstrate that energy efficiency relies on the balance between dynamic and leakage energies, with process variability playing a key role in both energy efficiency and robustness. We continue the study of energy-efficient design by broadening our scope to the architectural level. We discuss the energy benefits of techniques such as multiple-threshold CMOS (MTCMOS) and adaptive body biasing (ABB), and we also consider the performance benefits of multiprocessor design at ultralow supply voltages.

Low-power CMOS at Vdd = 4kT/q

Summary form only given. This paper reports a CMOS inverter active power-delay product of less than 0.1 fJ/stage at 25/spl deg/C and at Vdd=0.1 V. We believe this is the lowest reported. This is accomplished by using a novel technique to match NFET and PFET subthreshold currents and, thus, enable operation of a standard 1.5 V 180 nm CMOS technology in subthreshold at very low Vdd. This technique uses voltage feedback to the MOSFET wells to match the NFET off current (Ioffn) and PFET off current (Ioffp), significantly enhancing the manufacturability of CMOS subthreshold logic.

FinFET performance advantage at 22nm: An AC perspective

At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.

The current-carrying corner inherent to trench isolation

It is shown how the characteristics of the corner MOSFET inherent to trench isolation can be extracted from hardware measurements and how the corner device must be taken into account when extracting MOSFET channel characteristics. For NFETs it is found that the corners threshold voltage, substrate sensitivity, and sensitivity to well doping are all smaller than the channels. The results imply that for low-standby-power logic applications requiring high performance, it may become necessary to locally control the well doping at the corner. However, the corners reduced substrate sensitivity and width independence can provide a significant advantage in a DRAM cell.<<ETX>>

Energy optimality and variability in subthreshold design

Recent progress in the development of subthreshold circuit design techniques has created the opportunity for dramatic energy reductions in many applications. However, energy efficiency comes at the price of timing and energy variability due to process variations. We explore energy optimality in the subthreshold regime, discuss variability in this region, and highlight the energy and variability characteristics of a real subthreshold design

The effects of gate field on the leakage characteristics of heavily doped junctions

A gated-diode leakage-current mechanism is reported that is dominant below 4 V in ULSI (ultra-large-scale integration) gated-diode structures. The leakage mechanism has been fully characterized for gated junctions inherent in DRAM (dynamic random access memory) storage capacitor structures and the source-drain junctions of both PMOS (p-metal-oxide-semiconductor) and NMOS device structures. The salient features of the observed leakage current are that it is thermally activated and its magnitude increases exponentially with applied gate voltage. By making measurements at cryogenic temperatures it was possible to distinguish between the reported mechanism and that of band-to-band tunneling that occurs at higher applied voltages. A theoretical model is proposed that attributes the leakage mechanism to transport-limited thermal generation within the depleted space-charge region of the heavily doped side of junctions. An analytical expression derived from the proposed model is shown to be in excellent agreement with experimental results. >

GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications

Investigation of gate-induced drain leakage (GIDL) in thick-oxide dual-gate doped- and undoped-channel FinFET devices through 3-D process and device simulations is presented. For a given gate length (LG) and gate dielectric thickness, the placement and grading of the drain junction and the channel doping are shown to have a tremendous impact on GIDL. Suppression of GIDL by as much as two orders of magnitude can be realized by formation of steep underlapped junctions for both doped- and undoped-channel devices. The prospect of low leakage levels in doped-channel high- VT FinFETs makes them suitable for memory cell applications.

Channel doping impact on FinFETs for 22nm and beyond

The natural choice to achieve multiple threshold voltages (Vth) in fully-depleted devices is by choosing the appropriate gate workfunction for each device. However, this comes at the cost of significantly higher process complexity. The absence of a body contact in FinFETs and insensitivity to back-gate bias leaves the conventional channel doping approach as the most practical technique to achieve multiple Vth. This choice, however, introduces a variable that is usually not considered in the context of fully depleted devices. For the first time, we demonstrate a multiple Vth solution at relevant device geometries and gate pitch for the 22nm node. We investigated the impact of FinFET channel doping on relevant device parameters such as Tinv, mobility, electrostatic control and Vth mismatch. We also show that Vth extraction by the “constant current” method could mislead the DIBL analysis of devices with greatly different channel mobility.

Dual stress liner enhancement in hybrid orientation technology

Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I/sub DSat/ at 100 nA/um I/sub OFF/ for V/sub DD/=1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from [110] silicon and an additional 8% benefit due to the compressive MOL film.