Antonio La Manna

Measurements and Analysis of Substrate Noise Coupling in TSV-Based 3-D Integrated Circuits

Silicon substrates can be strategically isolated or unified among tiers in a through-silicon-via (TSV)-based 3-D integrated circuit (IC) structure, for the suppression of intertier substrate noise coupling or the reduction of grounding impedance of silicon substrates as a whole, respectively. A two-tier 3-D IC demonstrator in a 130-nm CMOS technology was successfully tested and analyzed with respect to intra and intertier substrate noise coupling. Each tier in the stack includes digital noise source circuits (NSs) and substrate noise monitors, and embodies in-place measurements of substrate noise coupling. An equivalent circuit unifies power and substrate networks of the tiers and simulates the frequency-domain response of substrate noise coupling. Measurements and calculation with the equivalent circuit are consistent for frequency dependency of substrate noise coupling in a 3-D IC demonstrator. Intratier propagation is dominant, while intertier coupling is insignificant for low-frequency substrate noise components. Intertier coupling becomes comparable with and finally overwhelms intratier coupling as the frequency of substrate noise components increases. Substrate noise coupling in a multitier chip stack is strongly impacted by the parasitic capacitance of TSVs, while that coupling becomes predictable with the equivalent circuit of the entire stack.

3D technology roadmap and status

The semiconductor industry is witnessing a major shift towards heterogeneous 3D integration. Whether companies are active in high performance or consumer markets systems, 3D offers a myriad of opportunities. We will review the different opportunities, indicate process availability and remaining challenges from both design and technology perspective.

Biocompatibility assessment of advanced wafer-level based chip encapsulation

Next generation implantable microsystem-based medical devices will have different packaging requirements than current implantable devices such as pace makers. While the packaging must remain biocompatible and provide a bi-directional diffusion barrier, it must also permit the biosensors, microelectrodes, etc to intimately interact with the extracellular environment. A CMOS compatible wafer level packaging strategy for die encapsulation has been developed and tested. TXRF measurements of 3T3 culture medium used in elution testing at physiological temperatures indicate the stack of PECVD diffusion barriers (SiC, SiN, SiO2) are effective in limiting Cu from leaching from the device. Additionally live-dead cell assays on in vitro co-cultures with both 3T3 fibroblasts and neonatal rat cardiomyocytes demonstrate the effectiveness of the different diffusion barrier stacks in preventing cytotoxic conditions.

Via-middle through-silicon via with integrated airgap to zero TSV-induced stress impact on device performance

In the study, we report for the first time a novel concept for the mitigation of the TSV-induced stress on the CMOS device performance. This solution consists in selectively integrating an airgap at the time of via-middle TSV processing. In addition to the expected benefits in term of stress management, this new approach is also cost effective, as the TSV processing steps, such as deep silicon etching, Cu electroplating, and chemical mechanical polishing remain unchanged. The processing development and the results of the morphological and electrical characterization are given in details in this study. All in all, TSV with integrated airgap is a very versatile building block for TSV integration in presence of stress sensitive next generation of CMOS devices.

An IC-centric biocompatible chip encapsulation fabrication process

Based on the requirements for miniaturization of a biocompatible package for medical implants, we derived a process flow for hermetic encapsulation of individual dies. In order to be cost-effective, wafer level based processing is used for this packaging flow. All processes are carried out using conventional clean room tools. Hermeticity of the individual dies or microsystems is ensured by using a stack of encapsulation layers, covering the individual dies. Furthermore, the die edges are sloped instead of straight, resulting in a better step coverage of the encapsulation layers. The total implantable device consists of various subdevices, hence assembly of these hermetical packaged subdevices is required, followed by a biocompatible metallization to connect the subdevices, and finally a global biocompatible embedding process is needed to obtain one single implantable device.

Thermo mechanical challenges for processing and packaging stacked ultrathin wafers

During the manufacturing of 3D stacked-die packaging structures, different operations such as micro bumps formation, underfilling, flip chip and overmold curing will introduce residual stresses, which will interact with subsequent service loads applied to the package and may also influence the growth of cracks in critical locations. In this work, the packaging of a 3D-RAM mounted on a logic die is simulated taking the thermal history into account by simulating the main process steps and by adapting the mechanical stiffness of the materials. The resulting stress/strain tensors are taken as initial condition of the following step and the mechanical properties of the new materials added to the process are adapted. The resulting stresses and strains at every step are extracted from the model to identify the most critical processing steps. A die to wafer approach is used for the stacking process as it allows the integration of heterogeneous and different die size. In this work we show the simulation results after each processing step for two die stacking approaches: (a) mold wafer reconstruction, (b) window wafer reconstruction. In the first case, high warpage is observed. In the second case, warpage is reduced but high stress concentration is observed in the logic die.

In-tier diagnosis of power domains in 3D TSV ICs

Power and substrate domains are strategically isolated or unified in heterogeneous 3D integration. In-tier probing circuitry provides accessibility to power delivery and substrate networks in a deep tier of a 3D chip stack and capability of diagnosing intra/inter tier coupling. A two-tier demonstrator was successfully tested in a 130 nm CMOS, 3D-SIC Cu TSV technology.

ESD protection design in active-lite interposer for 2.5 and 3D systems-in-package

Adding low-cost front-end processing to a passive interposer process flow enables the low-cost processing of diodes, SCRs and bipolar transistors. Using those devices in an ESD protection design allows moving a large part of the ESD protection from the stacked die to the interposer.

Fine pitch micro-bump Cu/Sn solid state diffusion bonding with and without surface planarization

3D integration requires a physical stacking of die onto another die while forming a permanent electrical and mechanical connection between the input/output pins of the devices. Low temperature stacking of dies for 3D integration has been gaining interest due to the thermal sensitivity of some advanced node devices such as DRAM. This paper presents a systematic study of Cu/Sn solid state diffusion bonding. This includes the use of bump surface conditioning and surface planarization. The Cu/Sn solid state diffusion bonding together with Cu TSV is used for making die to die vertical interconnection.