Philippe Soussan

3D stacked IC demonstration using a through Silicon Via First approach

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Through-silicon via and die stacking technologies for microsystems-integration

The highest integration density of microsystems can be obtained using a 3D-stacking approach, where each layer of the stack is realized using a different technology, which may include sensors, imagers, rf and MEMS technologies. A key challenge is however to perform such stacking in a cost-effective manner. In this paper, a novel 3D TSV and 3D stacking technologies will be presented. Application examples are MEMS packaging and heterogeneous integration of imaging devices.

3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding

In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using both Cu Through Silicon Vias (TSV) First and cost effective solution Die-to-Wafer Hybrid Collective bonding. The Cu TSV-First process is inserted between contact and M1. The top die is thinned down to 25µm and bonded to the landing wafer by Hybrid Bonding. Measurements and simulations of the power delay trade-offs of various 3D Ring Oscillator are provided as a demonstration of the relevance of such process route and of the design/simulation capabilities.

Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

A scalable generic Through Silicon Via (TSV) process is developed using spin-on dielectric polymer as isolation layer where deep annular trenches in Silicon are filled with the polymer. Following parameters are found to be affecting the polymer material spreading on the wafer surface and the filling performance: pre-treatments on the wafer surface, TSV density and physical properties of the polymer. Yielding TSV chains are measured on the fabricated wafers and the TSV resistance is found to be ≪100mΩ. It is a via-last TSV process which is applicable to any silicon technology.

3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 μm. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 μm ØTSV, 5 μm thick polymer liner, 25-μm-Ø Cu TSV, 50 μm deep TSV, and a 60 μm TSV pitch.

Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications

Ring-shaped silicon trenches with a depth of 50 were filled with different spin-on dielectric (SOD) polymers. Ultimately, the polymer should serve as deep trench isolation layers, also called liners, for 3-D wafer-level packaging through silicon vias (TSVs). TSVs allow the vertical stacking and interconnection of multiple devices. 3-D packaging is an emerging technology that can be an alternative solution to scaling issues in complementary metal oxide semiconductors. SODs with different electrical, chemical, and mechanical properties were tested. The filling was conducted using spin coating, which is a readily available technology. In order to improve the filling performances, a prewetting solvent was applied prior to coating. Contact angle measurements were carried out to assess the polymer wetting properties. Without prewetting, it was observed that too high an affinity for the wafer surface was probably detrimental. With prewetting, the wetting was improved but this did not significantly modify the filling itself. The filling was rather improved due to the mechanical action of the solvent. Overall, most of the SOD could successfully fill the trenches, however, stress-related delamination could almost always be detected at the polymer/silicon interface. A stress study was carried out by finite element modeling in order to address the delamination issue. It was concluded that the level of stress is mainly governed by the cure temperature and other mechanical properties. This paper concludes with some recommendations on the choice of an SOD for filling applications.

Temperature dependent electrical characteristics of through-si-via (TSV) interconnections

In this paper, we investigate the electrical behavior of TSV with increasing temperatures (25–150°C). TSV capacitance, leakage current and TSV resistance with varying temperatures are reported. TSV C-V characteristics are analyzed to extract the oxide charges. It is confirmed that the depletion behavior of TSV can be exploited to reduce TSV capacitance even at higher temperatures. In addition, lumped RC model of the TSV for circuit simulations is enhanced by incorporating measured TSV resistance and capacitance change due to temperature. The results are corroborated with the 2D/3D Ring Oscillator (RO) measurements at different temperatures.

Electrically yielding Collective Hybrid Bonding for 3D stacking of ICs

The production of non-monolithic 3D-systems by stacking and interconnecting components through substrate vias (TSVs) is intrinsically limited to the stacking of thin dies, typically ranging from 100µm down to 15µm. Since dies or wafers of such thickness are no longer rigid, it is an important requirement that the bond guarantees mechanical stability and rigidity to the thin stacked die or wafer. The route followed here combines the fixation of a thin wafer or die by means of a dielectric adhesive with the formation of a metallic interconnect. This process is called Hybrid Bonding. The introduction of a tacky polymer as an intermediate glue layer in the direct bonding scheme offers the possibility for die-to-wafer throughput optimization: the opportunity lies in the separation of die pick-and-place and bonding operations. This process is called Collective Hybrid Bonding. Two polymers have been selected (so called polymer A and polymer B) according to their reflowing and bonding properties, and a die pick and place procedure has been defined and optimized for each of them, allowing a fast and reliable operation. Moreover, electrical measurements of daisy chains showed a comparable and reproducible yield of 80% working chains up to 1000 TSVs.

Influence of the substrate on the lifetime of capacitive RF MEMS switches

We show for the first time that the substrate can influence the lifetime of capacitive RF MEMS switches. We demonstrate that the influence of the substrate should not be ignored. The influence of the environment on the lifetime of a switch is different when it is fabricated on two different substrates. We also present that a switch actuated with a DC voltage lower than the pull-in voltage can pull-in after some time. The goal of the performed experiment was to emphasize the charging of the substrate. The presented results help to understand the substrate charging problem.