Aravind Appaswamy

A Novel Device Architecture for SEU Mitigation: The Inverse-Mode Cascode SiGe HBT

We investigate, for the first time, the potential for SEE mitigation of a newly-developed device architecture in a 3rd generation high-speed SiGe platform. This new device architecture is termed the ¿inverse-mode cascode SiGe HBT¿ and is comprised of two standard devices sharing a buried subcollector and operated in a cascode configuration. Verification of the TID immunity is demonstrated using 10 keV X-rays, while an investigation of the SEE susceptibility is performed using a 36 MeV 16O ion. IBICC results show strong sensitivities to device bias with only marginal improvement when compared to a standard device; however, by providing a conductive path from the buried subcollector (C-Tap) to a voltage potential, almost all collected charge is induced on the C-Tap terminal instead of the collector terminal. These results are confirmed using full 3-D TCAD simulations which also provides insight into the physics of this new RHBD device architecture. The implications of biasing the C-Tap terminal in a circuit context are also addressed.

Impact of Scaling on the Inverse-Mode Operation of SiGe HBTs

The inverse-mode operational regime of silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) has to date been largely ignored and is typically dismissed as a viable possibility for circuit applications due to the general perception of its limited dc and ac performance capabilities. In this paper, the inverse-mode performance of four distinct generations of SiGe HBTs is investigated and is found to improve impressively with generational scaling. The physics behind these scaling-induced improvements is examined in detail using a combination of measurements and calibrated simulations. A novel lateral dependence of the inverse-mode base current is identified and is shown to potentially present new opportunities for even larger improvements in inverse-mode performance in SiGe HBTs. A record peak fT in inverse mode of 25 GHz is reported for a prototype fourth-generation device

The Effects of Proton and X-Ray Irradiation on the DC and AC Performance of Complementary (npn + pnp) SiGe HBTs on Thick-Film SOI

The impact of 63.3 MeV proton and 10 keV X-ray irradiation on the DC and AC performance of complementary SiGe HBTs on thick-film SOI is investigated. Proton and X-ray induced changes in the forward and inverse Gummel characteristics, the output characteristics, and avalanche multiplication are reported for both npn and pnp SiGe HBTs, at both room temperature (300 K) and at cryogenic temperatures (down to 30 K). Comparison of room temperature and cryogenic data suggests interface trap formation at two distinct physical locations in the transistors. Experimental data and calibrated TCAD simulations are used to compare the radiation response of both thick-film SOI devices and thin-film SOI SiGe HBTs.

Optimizing Inverse-Mode SiGe HBTs for Immunity to Heavy-Ion-Induced Single-Event Upset

Inverse-mode (collector-up) operation is proposed as a solution to the single-event-upset susceptibility observed in commercially available bulk silicon-germanium heterojunction bipolar transistors. Inverse-mode performance optimization techniques, which require no process changes or added lithographic masks, are demonstrated, yielding inverse-mode transistor performance capable of supporting gigabit-per-second digital logic needed in space-based communication systems.

A New Current-Sweep Method for Assessing the Mixed-Mode Damage Spectrum of SiGe HBTs

We present a new ldquocurrent-sweeprdquo stress methodology for quantitatively assessing the mixed-mode reliability (simultaneous application of high current and high voltage) of advanced silicon-germanium (SiGe) HBTs. This electrical-stress methodology allows one to quickly obtain the complete ldquodamage spectrumrdquo of a given device from a particular technology platform, enabling better understanding of the complex voltage, current, and temperature interdependence associated with electrical stress and burn-in of advanced transistors. We consistently observe three distinct regions of mixed-mode damage in SiGe HBTs and find that hot-carrier-induced damage can be introduced into SiGe HBTs under surprisingly modest mixed-mode-stress conditions. For more aggressively scaled technology generations, a larger percentage of hot carriers generated in the collector-base junction are able to travel to and hence damage the emitter-base (EB) spacer, leading to enhanced forward-mode base-current leakage under stress. A new self-heating-induced mixed-mode-annealing effect is observed for the first time under specific high-voltage- and high-current-stress conditions, and a new damage mechanism is observed under very high-voltage and high-current conditions. Finally, as an example of the utility of our stress methodology, we quantify the composite mixed-mode damage spectrum of a commercial third-generation (200 GHz) SiGe HBT. We find that if devices are stressed with either voltage or current alone during burn-in, they can easily withstand extreme overstress conditions. Unfortunately, devices can easily be damaged when stressed with a combination of stress voltage and current, and this has significant implications for the lifetime prediction under realistic mixed-signal-circuit operating conditions.

Understanding Radiation- and Hot Carrier-Induced Damage Processes in SiGe HBTs Using Mixed-Mode Electrical Stress

Using mixed-mode annealing to help evaluate the responses of modern bipolar transistors, we compare the damage processes associated with X-ray irradiation-induced and hot carrier-induced damage in SiGe HBTs. Stress and radiation measurements indicate that the by-products of both X-ray irradiation-induced and hot carrier-induced trap reactions are identical. We use calculations to better understand the operative damage mechanisms, and find that a hydrogen reaction-diffusion model can predict the observed characteristics of our measurements. Calculations indicate that the transport of hydrogen molecules inside the emitter-base oxides determines the trap generation and recovery processes.

Junction Isolation Single Event Radiation Hardening of a 200 GHz SiGe:C HBT Technology Without Deep Trench Isolation

We investigate a novel implementation of junction isolation to harden a 200 GHz SiGe:C HBT technology without deep trench isolation against single event effects. The inclusion of isolation is shown to have no effect on the dc or ac performance of the nominal device, and likewise does not reduce the HBTs inherent tolerance to TID radiation exposure on the order of a Mrad. A 69% reduction in total integrated charge collection across a slice through the center of the device was achieved. In addition, a 26% reduction in collected charge is reported for strikes to the center of the emitter. 3-D NanoTCAD simulations are performed on RHBD and control device models yielding a good match to measured results for strikes from the emitter center to 8 ¿m away. This result represents one of the most effective transistor layout-level RHBD approaches demonstrated to date in SiGe.

Influence of Interface Traps on the Temperature Sensitivity of MOSFET Drain-Current Variations

The temperature sensitivity of drain-current variations in the subthreshold regime of MOSFET operation is analyzed through TCAD simulations and device measurements. Interface traps are determined to be the dominant factor in increasing the temperature sensitivity of drain-current differences in weak inversion. The variability caused by interface defects has significant implications on the reliability of MOSFET-based circuits intended for extreme-environment applications.

Impact of deep trench isolation on advanced SiGe HBT reliability in radiation environments

We investigate, for the first time, the impact of deep trench isolation on the total ionizing dose (TID) and single event upset (SEU) tolerance of advanced SiGe HBTs. We employ a combination of 63MeV protons, 10keV X-rays, and 36MeV oxygen ion microbeam irradiation and compare a 3rd generation, high-performance (HP), deep-trench isolated, SiGe BiCMOS platform with its cost-performance (CP) variant without deeptrenches. Although the CP SiGe HBTs are shown to be more susceptible to TID damage, the elevated damage is not attributed to variations in deep trench isolation (DTI), but to spacer oxide differences. CP SiGe HBTs are surprisingly found to offer a potential built-in self-mitigation mechanism for SEU, which is a direct result of the influence of the deep trench isolation on the charge collection dynamics associated with ion strikes. Calibrated, full 3D ion strike TCAD simulations are employed to explain the results, revealing substantial enhancement of radial charge diffusion for structures implemented with little to no deep trench. Mitigation of charge collection events are found to occur for emitter-center strikes for devices with limited/eliminated DTI with the caveat of larger collection for outside-DTI ion strikes.

Modeling mixed-mode DC and RF stress in SiGe HBT power amplifiers

The degradation of SiGe HBTs due to mixed-mode DC and RF stress (simultaneous application of high current and voltage) has been modeled for the first time. State-of-the-art 200 GHz SiGe HBTs were first characterized, and then DC and RF stressed. Using TCAD simulations and calculations based upon a reaction-diffusion model, the excess base current due to stress was modeled as a function of the stress current and voltage. This physics-based stress model was then designed as a sub-circuit in Cadence, and incorporated into a cascode SiGe PA design to predict the DC and RF stress-induced excess base current. Predicted degradation is in agreement with RF stress results.