J. H. Sim

Mechanism of Electron Trapping and Characteristics of Traps in

Electron trapping in high- gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping). Characteristics of the electron traps extracted based on the proposed model are in good agreement with the calculated properties of the negatively charged oxygen vacancies. The model successfully describes low-temperature threshold voltage instability in NMOS transistors with /TiN gate stacks.

\hbox{HfO}_{2}

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.

Gate Stacks

Electron trapping in high-k gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the pre-existing defects (fast trapping) and temperature-activated migration of trapped electrons to unoccupied traps (slow trapping). The proposed model successfully describes low temperature threshold voltage instability in NMOS transistors with HfO 2/TiN gate stacks

Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)

Fast electron trapping in high-k gate dielectrics is shown to effectively increase the magnitude of the threshold voltage during the dc measurements of the drain current, which leads to underestimation of the intrinsic channel carrier mobility. An approach based on the pulse Id-Vg technique is proposed to estimate a correction factor to the dc mobility.

Intrinsic Threshold Voltage Instability of the HFO2 NMOS Transistors

Electron traps in ALD and MOCVD HfO 2 and HfSiO high-k dielectrics were investigated using both conventional DC and pulse measurements. It was found that the traps in the gate stack could be associated with defects of different activation energies and capture cross-sections. This points to potentially different origins of the electrically active defects, which can be either intrinsic or process-related. Structural non-uniformity of the high-k film, associated with grain formation and phase separation, may lead to variation of electrical properties of the gate dielectric along the transistor channel. Effects of such dielectric non-uniformity, as well as electron trapping, on the measured transistor mobility were evaluated.

Mobility evaluation in transistors with charge-trapping gate dielectrics

We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO/sub 2/ gate dielectric. The wet etch of TaSiN had a minimal impact on HfO/sub 2/ (/spl Delta/EOT<1/spl Aring/). A plasma etch process has been developed to etch Ru/TaN/Poly (PMOS) and TaSiN/Ru/TaN/Poly (NMOS) gate stacks simultaneously. Well behaved dual metal gate CMOS transistors have been demonstrated with L/sub g/ down to 85nm.

Effects of Structural Properties of Hf-Based Gate Stack on Transistor Performance

The instability of threshold voltage in high-/spl kappa//metal gate devices is studied with a focus on the separation of reversible charge trapping from other phenomena that may contribute to time dependence of the threshold voltage during a constant voltage stress. Data on the stress cycles of opposite polarity on both pMOS and nMOS transistor suggests that trapping/detrapping at the deep bandgap states contributes to threshold voltage instability in the pMOS devices. It is found that under the same electric field stress conditions, threshold voltage changes in pMOS and nMOS devices are nearly identical.

Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric

We report a high performance NFET with a HfO/sub 2//TiN gate stack showing high field (1 MV/cm) DC mobility of 194 cm/sup 2//V-s (80% univ. SiO/sub 2/) and peak DC mobility of 239 cm/sup 2//V-s at EOT=9.5/spl Aring/. These mobility results are among the best reported for HfO/sub 2/ with sub-10 /spl Aring/ EOT and represent a potential gate dielectric solution for 45 nm CMOS technologies. A 2/spl times/ mobility improvement was realized by thinning HfO/sub 2/ from T/sub phys/=4.0 nm to 2.0 nm. The mechanism for mobility improvement is shown to be reduced transient charge trapping. Issues associated with scaling HfO/sub 2/ including film continuity, density and growth incubation are studied with low energy ion scattering (LEIS), X-ray reflectivity (XRR) and Rutherford backscattering (RBS) and indicate atomic layer deposition (ALD) HfO/sub 2/ can scale below T/sub phys/= 2.0 nm. While the mobility advancement with 2.0 nm HfO/sub 2/ is important, an additional concurrent advancement is improved V/sub t/ stability. Constant voltage stress results show /spl Delta/V/sub t/ improves 2/spl times/ after 1000s stress at 1.8V as thickness is reduced in the range 2.0-4.0 nm.

Electrical observation of deep traps in high-/spl kappa//metal gate stack transistors

The evaluation of the instability of the threshold voltage in high-k gate stack structures is of paramount importance in assessing the reliability of next generation FETs. In the case of SiO/sub 2/ gate dielectric PMOS transistors, this instability, known as NBTI, has been attributed to the hole-assisted dissociation of the hydrogen that passivates dangling bonds at the interface with the Si substrate. However, in hafnium-based gate stacks, evaluation of the NBTI phenomenon is complicated by the charge trapping process, which was shown to occur reversibly on pre-existing defects in NMOS devices. In this report, we examine the cycle dependence of negative gate stress and positive gate de-trapping on PMOS high-k/metal gate transistors. The threshold voltage instability is found to be due mainly to charge trapping and de-trapping of both shallow and deep electron traps in the high-k dielectric. There is minimal change in the interface quality with negative bias stress, and a similar detrapping nature is found for NMOS devices with a comparable electric field.

Mobility enhancement of high-k gate stacks through reduced transient charging

We report on the plasma induced damage in the TiN/HfSiO/sub 4/ gate stack, and, specifically, its impact on pMOSFETs. Plasma assisted deposition processes after the gate stack etch step appear to cause most plasma damage, manifested by greater degradation of the plate antenna structures (area intensive) compared to comb antennas (perimeter intensive). The transient charge trapping behavior of the HfSiO/sub 4/ film seems to prevent destructive dielectric breakdown. Electrical stress could generate additional traps in the film damaged by the plasma process.