Tom C. Lee

Reliability challenges for copper interconnects

Abstract In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low- k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.

Characterization and reliability of TaN thin film resistors

TAN resistors are commonly used in RFIC applications and are gaining acceptance in traditional CMOS designs. TAN materials, frequently used in fabrication of Cu interconnects can easily be applied to the fabrication of thin film resistors. Deposition and integration of the films may be well controlled to produce a high precision resistor, and the temperature coefficient of resistance (TCR) characteristics of the film make it ideally suited for application across a large temperature range. While the time zero characteristics of the device are well understood, of equal importance are the device reliability properties. In this paper traditional film characteristics such as resistance distributions and TCR characteristics are presented. A voltage ramp stress is employed to identify the critical current A constant voltage stress at high temperature is utilized for reliability evaluation. Based on the stress results, a reliability degradation model is derived to express the relationship between stress condition, resistance change, and lifetime. The results demonstrate that the TAN thin film resistor is reliable over traditional IC operating ranges. While TAN resistors are robust, application conditions of the resistor typically result in significant resistive joule heating. The joule heating effects on the resistor are included in the resistor degradation model. The effects of the joule heating on reliability for neighboring structures must also be considered. The effective result is that the maximum allowed use current of the resistor might be dictated by the resistive joule heating and not necessarily the resistor reliability itself. The effect of the joule heating on neighboring structures is a subject itself and will not be covered in this paper.

Line depletion electromigration characteristics of Cu interconnects

Specific details of fabrication process and geometry of Cu interconnects result in different electromigration (EM) fail modes. This paper discusses EM characteristics of line depletion mode stress, i.e. for the case of electrons flowing into a Cu line through a Cu diffusion barrier to cause voiding in the line. For electrons flowing from a W via, for example to a Cu line above, redundancy exists due to the overlap of line bottom liner over the top of the via. When electrons flow from a via above down to a Cu line, the redundancy characteristics can be very different for different via/line layouts and result in different EM fail distributions. The solid contact between via and the liner of the line below can result in tight fail distributions, while weak contact or lack of contact between the via and the liner of the line below can cause broad (high sigma), or even multi-mode fail distributions. A few examples and their implications on robust interconnect design are presented. The relation between void size and liner redundancy characteristics is also discussed.Specific details of both fabrication process and geometry of Cu interconnects result in different electromigration (EM) fail modes. This paper discusses EM characteristics of line depletion stress, i.e., for the case of electrons flowing from a via above into a Cu line through a Cu diffusion barrier to cause voiding in the line. For electrons flowing from a W via, for example to a Cu line above, electrical redundancy (i.e., a current shunt layer) exists due to the overlap of line bottom liner over the top of the via, such that a current path still exists in the event that the Cu is removed. When electrons flow from a via above down to a Cu line, the redundancy characteristics can be very different for different via/line layouts, and can result in different EM fail distributions. The solid contact between via above and the liner of the line below can result in tight fail distributions, while weak contact or lack of contact between the via above and the liner of the line below can cause broad (high sigma), or even multimode fail distributions. A few examples and their implications on robust interconnect design are presented. The relation between void size and liner redundancy characteristics is also discussed.

Comparison of isothermal, constant current and SWEAT wafer level EM testing methods

In this paper, we present data from three wafer level electromigration test techniques, isothermal, constant current, and standard wafer level electromigration accelerated test (SWEAT), and compare various aspects of the data. The isothermal method keeps the test line at a constant temperature by monitoring line resistance during test. The constant current method simply applies a constant current of the same magnitude to all lines, without making any adjustments for individual geometric differences. The SWEAT method holds the time to failure constant by using Blacks equation to determine the applied current needed to bring about the chosen failure time. Six different line widths ranging from 0.150 to 4.285 /spl mu/m of AlCu metallization were stressed by all three methods, at temperatures from 300 to 380/spl deg/C in 10/spl deg/C steps.

Reliability challenges for advanced copper interconnects: Electromigration and time-dependent dielectric breakdown (TDDB)

Ensuring the reliability of Cu interconnects becomes more challenging as device dimensions shrink, because of the smaller dimensions and because of the weaker mechanical properties of the low-k material. In this report, we will focus on electromigration and time dependent dielectric breakdown (TDDB) in Cu interconnect structures.

Reliability Challenges in Copper Metallizations arising with the PVD Resputter Liner Engineering for 65nm and Beyond

In this paper the influence of liner deposition parameters on the reliability of 65nm copper metallizations have been investigated for two different deposition sequences. The use of resputter liners in the 65nm generation turned out to change the via-voiding failure mode qualitatively from voiding at the very via-bottom to void nucleation at mid-half of the via. In addition, the resputter intensity and liner thickness have a quantitative impact on the electromigration (EM) failure times and stress migration (SM) failure rates. For a given liner thickness an increasing resputter intensity turned out to improve the overall reliability as a result of a more pronounced anchoring of the via within the metal line underneath. In terms of the liner thickness, thinner barriers yield in general reduced failure times. However, this loss can be compensated at least partially by adjusting the resputter intensity with repsect to the specific liner thickness

Reliability of Copper Interconnects: Stress-Induced Voids

Stress-induced voids can form in Cu interconnects, due to either thermal expansion mismatch between the metal and the dielectric or due to confined grain growth in the Cu. The fail rate due to stress-induced voids increases as device dimensions decrease, because the critical void size to cause a fail decreases. Good process control is required for trench and via profiles, barrier and seed layer coverage, Cu fill, and cap layer adhesion, to prevent fails from stress-induced voids.

Constant-Current Wafer-Level Electromigration Test: Normalization of Data for Production Monitoring

Reliability monitoring is an important part of process control in high-volume production. For metallization, a wafer-level electromigration (WL-EM) test is usually the method of choice to get a good indication of process variation. Different WL-EM methods have been reported, including a constant current method, the SWEAT test, the isothermal test, and the breakdown energy of metal test. The method used in this paper uses the ramping procedure for the isothermal test to achieve the target temperature, but then hold the current constant without feedback correction once the target temperature has been achieved. We present practical normalization procedures to ensure an appropriate wafer-to-wafer comparison that is independent of variation in cross-sectional area as well as of the initial resistance spread. The measurements were performed on a commercially available 200-mm multiside probe station using custom software to implement the current ramp and resistance measurement. Test conditions were achieved through Joule heating; the test structures used were 800-mum-long single lines (no vias) in metal 1 to metal 3, varying in width from 0.14 to 10 mum. Due to variations in the hardware and in the temperature coefficient of resistance (TCR), several normalization steps (described below) were necessary in demonstrating reasonable and expected trends in the data. Results of the analysis suggest that the appropriate value for the current density exponent for this test methodology is two, and they also verify that the TCR varies with linewidth, decreasing as linewidth decreases.

Technology Reliability Qualification of a 65nm CMOS Cu/Low-k BEOL Interconnect

During the development and qualification of a 300mm low-k/Cu back end of line (BEOL) technology, the long-term reliability of such interconnects including low-k time-dependent dielectric breakdown (TDDB), Cu electromigration (EM), Cu stress migration (SM), and Cu/low-k thermal behavior are rapidly becoming one of the most critical challenges. In this paper, a comprehensive reliability evaluation for 65nm Cu/low-k interconnects is reported and various reliability issues associated with process integration and material optimization during initial development stage are discussed. Finally, we demonstrate that with careful process and materials optimization, a superior interconnect reliability performance at the 65nm technology node can be achieved for 300mm fabrication. The projected reliability lifetimes of TDDB, EM, and SM meet the most stringent reliability targets and criteria

Electromigration study of Al and Cu metallization using WLR isothermal method

Wafer level electromigration behavior of copper and aluminum using isothermal stress was investigated in this paper. Lifetime, lognormal standard deviation, and activation energy were evaluated as a function of stress temperature as well as line width. Temperature dependence of the embedded 2D thermal behavior was modeled via the initial stress current versus the initial resistance correlations. The mass transport mechanisms in the highly accelerated wafer level electromigration were observed to be the same as those in moderately accelerated conventional package level electromigration for both Cu-based and Al-based systems.