Benjamen Michael Rathsack

Fabrication of 28nm pitch Si fins with DSA lithography

Directed Self-Assembly (DSA), as an extension of current state-of-the-art photolithography, has demonstrated the capability for patterning with resolution and cost effectiveness beyond the capability of other techniques. Previous studies of DSA have reported encouraging benchmarks in defect density and throughput capability for the patterning step, and such results provide a foundation for our ongoing efforts to integrate the DSA patterning step into a robust process for fabricating device layers. Here we provide a status report on the integration of two chemoepitaxy DSA patterning methods for the fabrication of 28nm pitch Si fin arrays. In addition to the requirements for a robust pattern transfer process, it is also important to understand the pattern design limitations that are associated with DSA. We discuss some of the challenges and opportunities associated with developing efficient device designs that take advantage of the capabilities of DSA.

Aerial image degradation effects due to imperfect sidewall profiles of EAPSM mask for 130-nm device node: 3D EMF simulations and wafer printing results

As our chip producing industry gearing up for mass production of 130nm device technology node, use of EAPSM (Embedded Attenuated Phase Shift Mask) technology in the critical pattern levels became unavoidable because of the low k1 factor lithography involved. However, this 2-layer EAPSM material (attenuator material covered with Chrome) requires two distinctively separate lithography/etch processes needed to be carried out. These added complexities of processes are prone to degradation of the absorber materials (MoSi) sidewall leading to imperfect sidewall profiles (top corner rounding, off-normal sidewall angle, etching intrusion into quartz substrate, footing, . . . etc.). These imperfections of sidewall cause aerial image degradations thus reduce effectiveness of full benefits of PSM technology. In this paper, we discuss our findings of mask level aerial image degradation dependency on EAPSM material sidewall imperfections, which result from immature mask making processes, and assessments of its effects on pattern transfer onto wafer level using 3&2D EMF and subsequent lithography simulations. The results were then, compared to actual wafer results for the wafer level printing confirmation to the simulation results. We distinguish consequence of resulting aerial image differences between EMF simulations vs. Kirchhoff approximation (treatment of absorber to be infinitely thin layer; normally used in conventional lithography simulations) in the KrF EAPSM material (MoSi). Furthermore, we have carried out look-ahead assessments for ArF (193nm) lithography using ArF EAPSM material (MoSiON) and made association between the sidewall profile variations and CD uniformity performance of EAPSM. We will make case that 3D EMF capability consideration is important in the low k1 factor lithography simulations.

CD variations from nontrivial mask-related factors

Mask critical dimension (CD) control relies on advanced write tools and resist processes. However, a specified write tool and process does not necessarily guarantee high mask quality. As the mask feature size shrinks to below 500 nm, there are other mask-related factors that can also significantly affect the mask performance. This paper discusses the impact of those non-trivial factors, such as mask writing tool and process control, calibration of mask CD metrology, blank quality of attenuated phase shift mask (ATPSM), pellicle degradation due to 193 nm laser irradiation, and profile of mask features, etc.