Bernard J. Roman

Practicing extension of 248-nm DUV optical lithography using trim-mask PSM

It is becoming increasingly clear that semiconductor manufacturers must rise to the challenge of extending optical microlithography beyond what is forecast by the current SIA roadmap. Capabilities must be developed that allow the use of conventional exposure methods beyond their designed capabilities. This is driven in part by the desire to keep up with the predictions of Moores law. Additional motivation for implementing optical extension methods is provided by the need for workable alternatives in the event that manufacturing capable post-optical lithography is delayed beyond 2003. Major programs are in place at semiconductor manufacturers, development organization, and EDA software providers to continue optical microlithography far past what were once thought to be recognized limits. This paper details efforts undertaken by Motorola to produce functional high density silicon devices with sub-eighth micron transistor gates using DUV microlithography. The preferred enhancement technique discussed here utilizes complementary or dual-exposure trim-mask PSM which incorporates a combined exposure of both Levenson hard shifter and binary trim masks.

Ring test aberration determination and device lithography correlation

The exposure tool is a critical enabler to continue improving the packing density and transistor speed in the semiconductor industry. In addition to increasing resolution (improving packing density), a scanner is expected to provide tight linewidth control across the chip, ACLV (transistor speed). An important component of ACLV is lens aberrations. Recently techniques that allow the measurement in-situ of aberrations using Zernike coefficients have become available. We have measured the first 25 Zernike coefficients in two ASML PAS 500/700D DUV Step & Scan systems. The measured Zernikes are in agreement with PMI (Phase Measurement Interferometry) data collected at the lens manufacturer within 3.8 nm or less. We find good agreement between the variation of the Z5 (first order astigmatism) coefficient and the optimum focus offset between horizontal and vertical lines measured using FOCAL. There is also good agreement between Z5 and the linewidth difference between 160 nm horizontal and vertical lines with a 330 nm pitch. The lines were printed using an NA equals 0.68, (sigma) equals 0.70 on 3,800 angstrom of resist on top of an inorganic BARC. We find good correlation between the Z7 coefficient (first order coma) and linewidth variation across the slit. We also found that the effect of the aberrations as measured by linewidth range is a function of pitch. Linewidth range decreases as the duty ratio increases, reaching a minimum at a duty ratio of 1:1.44, and then increases again as the lines become isolated. This is surprising because these intermediate pitches also have the smallest focus-exposure window. We conclude that knowing the Zernike coefficients provides us with a very powerful tool to characterize our exposure tools. However to fully realize the benefit of this new tool we must improve the accuracy of our simulation tools.

Development of a sub-100-nm integrated imaging system using chromeless phase-shifting imaging with very high NA KrF exposure and off-axis illumination

Examining features of varying pitch imaged using phase-shifting masks shows a pitch dependence on the transmission best suited for optimum imaging. The reason for this deals with the relative magnitude of the zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and 180-degree phase-shifted regions. Subsequently, some of the diffraction orders are collected and projected to form the image of the object. Chromeless Phase-Shift Lithography (CPL) deals with using halftoning structures to manipulate these relative magnitudes of these diffraction orders to ultimately construct the desired projected image. A key feature of CPL is that with the ability to manipulate the diffraction orders, a single weak phase-shifting mask can be made to emulate any weak phase-shifting mask and therefore the optimal imaging condition of any pattern can be placed on a single mask regardless of the type of weak phase-shifter that produces that result. In addition, these structures are used to render the plurality of size, shape and pitch such that the formed images produce their respective desired size and shape with sufficient image process tolerance. These images are typically made under identical exposure conditions, but not limited to single exposure condition. These halftoning structures can be used exterior, as assist features, or interior to the primary feature. These structures can range in transmission from 0% to 100% and they can be phase-shifted relative to the primary features or not. Thus CPL deals with the design, layout, and utilization of transparent and semi-transparent phase-shift masks and their use in an integrated imaging solution of exposure tool, mask and the photoresist recording media. This paper describes the method of diffraction matching, provides an example and reviews some experimental data using high numerical aperture KrF exposure.

0.25-μm logic manufacturability using practical 2D optical proximity correction

Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of- the-art 0.25 micrometer random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data improvements in reticle manufacturability, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.

Application of CPL reticle technology for the 65- and 50-nm node

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

Re-evaluating simple lambda-based design rules for low-K1 lithography process control

Due to the continuing decrease of the Rayleigh lithographic K1 factor used in advanced semiconductor technology, the non- linearity between designed and printed circuit images continues to increase. This increasing non-linearity has significant implications for the layout design rules with advanced technology. Recently, industry pundits have speculated that lithographic K1 factors can go far below current value. This paper aims to understand the impact of low K1 lithography upon a set of basic, company independent, layout design rules, the lambda based rules proposed by Mead and Conway. The results show that even with the use of aggressive optical proximity correction (OPC) techniques, significant changes in layout design rules will have to be made in order to extend lithographic capability to the low K1 regime.

Characterization of CD control for sub-0.18 μm lithographic patterning

It is well known that systematic within-chip dimension (CD) errors can strongly influence product yield and performance, especially in the case of microprocessors. It has been shown that this across chip linewidth variation (ACLV) dominates the CD error budge, and is comprised of multiple systematic and random effects, including substrate reflectivity, reticle CD errors, feature proximity, and lens aberrations. These effects have material, equipment, and process dependencies, with the results being that significant ACLV differences between nominally identical tools/processes can in some cases be observed. We present here a new analysis approach which allows for optimization of exposure/defocus conditions to minimize overall CD errors for a given process. Emphasis is on control of [(mean) + 3 sigma] of CD errors for a given exposure/defocus conditions. Input metrology data is obtained from electrical resistance probing, and data is presented for multiple 248 nm DUV processes and tools with CD ground rules ranging from 180 nm to 140 nm.

Full-field CD control for sub-0.20-μm patterning

DUV scanning exposure systems have been steadily gaining market acceptance for the past five years, and soon, all major suppliers will offer 248-nm scanning tools. One of the major reasons for the emergence of this technology has been the purported improvement in critical dimension (CD) uniformity across the scanned field versus what can be realized in a full field stepper. Using high precision electrical resistance CD metrology, we have characterized the across field CD control capability of several DUV scanning tools and DUV steppers. Analysis is carried out through focus for multiple linetypes representing various orientations and nearest-neighbor proximities. Where possible, different NA/(sigma) combinations are examined as well. Surprisingly good full field sub-0.20 micrometers CD control is obtained even for 0.50 NA, and higher NA allows for non zero process latitude at 0.14 micrometers geometries. While it was initially anticipated that 193 nm ArF lithography would be required for 0.18 micrometers technology manufacturing, it has become apparent that 248 nm lithography will be employed for these groundrules, particularly for logic applications with predominantly semi-isolated features.

Plasma antireflective coating optimization using enhanced reflectivity modeling

An improved method is presented for the optimization of plasma deposited bottom inorganic anti-reflective coatings (ARCs). These ARCs have shown the capability to improve photolithography profess margins through reduction of substrate reflectivity while meeting integration issues. However, the ability to vary plasma ARC optical properties through deposition conditions has led to increased complexity of film stack optimization. We present simple but effective enhanced modeling methods for reducing the effort required to properly tune plasma ARC optical conditions and optimize complex films tacks incorporating these materials.

The application of CPL reticle technology for the 0.045-mm node

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.