Michael E. Kling

Practicing extension of 248-nm DUV optical lithography using trim-mask PSM

It is becoming increasingly clear that semiconductor manufacturers must rise to the challenge of extending optical microlithography beyond what is forecast by the current SIA roadmap. Capabilities must be developed that allow the use of conventional exposure methods beyond their designed capabilities. This is driven in part by the desire to keep up with the predictions of Moores law. Additional motivation for implementing optical extension methods is provided by the need for workable alternatives in the event that manufacturing capable post-optical lithography is delayed beyond 2003. Major programs are in place at semiconductor manufacturers, development organization, and EDA software providers to continue optical microlithography far past what were once thought to be recognized limits. This paper details efforts undertaken by Motorola to produce functional high density silicon devices with sub-eighth micron transistor gates using DUV microlithography. The preferred enhancement technique discussed here utilizes complementary or dual-exposure trim-mask PSM which incorporates a combined exposure of both Levenson hard shifter and binary trim masks.

0.25-μm logic manufacturability using practical 2D optical proximity correction

Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of- the-art 0.25 micrometer random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data improvements in reticle manufacturability, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.

Effects of complementary phase-shift imaging on gate CD control

Gate patterning has always been held to tight specifications for CD variation compared to other layers. Specifically, the gate layer is more concerned with the total CD variations including Across Chip Linewidth Variation (ACLV), Across Wafer Linewidth Variation (AWLV), CD variation through pitch (Proximity bias), than other layers. Therefore, complementary phase shift (c:PSM) imaging has been introduced at the gate layer under the assumption that it will reduce the total CD variation compared to binary imaging. However, c:PSM data conversion of random logic can introduce additional biases that also impact CD control. These new biases include CD variation as a function of shadow size, reticle-to-reticle overlay error, shifter width, and shifter height (a function of the transistor width and the shifter extension). This paper will show the improvements in ACLV and AWLV using c:PSM. This paper will also look at the increase in the proximity bias for c:PSM compared to binary imaging and show results for implementing a 1-D OPC correction on the phase shift reticle. In addition, this paper will also look at the magnitude of the various additional c:PSM biases mentioned. This paper will discuss the interaction of the different phase shift conversion input parameters for complex random logic and the limitations they impose on how tight we can make the final CD distribution. Finally, since c:PSM allows for selective sizing of CDs over active and over field, a brief discussion will also be given for the CD control of the complementary binary reticle.

Characterization of CD control for sub-0.18 μm lithographic patterning

It is well known that systematic within-chip dimension (CD) errors can strongly influence product yield and performance, especially in the case of microprocessors. It has been shown that this across chip linewidth variation (ACLV) dominates the CD error budge, and is comprised of multiple systematic and random effects, including substrate reflectivity, reticle CD errors, feature proximity, and lens aberrations. These effects have material, equipment, and process dependencies, with the results being that significant ACLV differences between nominally identical tools/processes can in some cases be observed. We present here a new analysis approach which allows for optimization of exposure/defocus conditions to minimize overall CD errors for a given process. Emphasis is on control of [(mean) + 3 sigma] of CD errors for a given exposure/defocus conditions. Input metrology data is obtained from electrical resistance probing, and data is presented for multiple 248 nm DUV processes and tools with CD ground rules ranging from 180 nm to 140 nm.

Manufacturability of subwavelength features using reticle and substrate enhancements

This paper uses simulation and experiment to study near resolution limit patterning of contacts and damascene trenches using conventional i-line lithography. Special attention is paid to the requirements for substrate control. The patterning behavior is compared to DUV lithography results. We also evaluate the cost-of-process for an i-line process using substrate and optical enhancements compared to a standard 248 nm DUV process.

Cost analysis of 4x and 6x 9-in. reticles for future lithography

Standardizing on reticle size is critical for semiconductor tool manufacturers and the semiconductor industry as a whole. The advantages of large reticles are well known: larger die and increased throughput. Although predictions of extremely large die have not yet been realized, the throughput implications remain valid. As large reticles have the potential to increase throughput, some proponents view them as potential cost savers. This work examines the implications of migrating from todays standard 6-inch reticles to 9-inch reticles. It explores the factors that drive reticle cost, and describes why larger reticles should cost more. The paper also describes the cost benefit of implementing larger masks. Comparing the expected cost of building the reticle to the potential cost savings of using the reticle in production provides significant insight into the problem of selecting the optimal reticle size. Finally, the paper presents an analysis of the impact of 6X reduction systems on the selection of reticle size.