Binqiang Shi

A low power 72.8 GHz static frequency divider implemented in AlInAs/InGaAs HBT IC technology

We report a 72.8 GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350 mV logic swing at less than 0 dBm input power up to a maximum clock rate of 63 GHz and requires 86 dBm of input power at the minimum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1 V power supply. To our knowledge this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is also the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1 V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power delay product for a static divider operating above 30 GHz in any technology.

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with f/sub t/>250 GHz and DHBT with f/sub t/>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.

A submicrometer 252 GHz f/sub T/ and 283 GHz f/sub MAX/ InP DHBT with reduced C/sub BC/ using selectively implanted buried subcollector (SIBS)

The selectively implanted buried subcollector (SIBS) is a method to decouple the intrinsic and extrinsic C/sub BC/ of InP-based double-heterojunction bipolar transistors (DHBTs). Similar to the selectively implanted collector (SIC) used in Si-based bipolar junction transistors (BJTs) and HBTs, ion implantation is used to create a N+ region in the collector directly under the emitter. By moving the subcollector boundary closer to the BC junction, SIBS allows the intrinsic collector to be thin, reducing /spl tau//sub C/, while simultaneously allowing the extrinsic collector to be thick, reducing C/sub BC/. For a 0.35 /spl times/ 6 /spl mu/m/sup 2/ emitter InP-based DHBT with a SIBS, 6 fF total C/sub BC/ and >6 V BV/sub CBO/ were obtained with a 110-nm intrinsic collector thickness. A maximum f/sub T/ of 252 GHz and f/sub MAX/ of 283 GHz were obtained at a V/sub CE/ of 1.6 V and I/sub C/ of 7.52 mA. Despite ion implantation and materials regrowth during device fabrication, a base and collector current ideality factor of /spl sim/2.0 and /spl sim/1.4, respectively, at an I/sub C/ of 100 /spl mu/A, and a peak dc /spl beta/ of 36 were measured.

Effects of device design on InP-based HBT thermal resistance

The thermal resistance of InP-based single and double heterojunction bipolar transistors has been measured. The double heterojunction bipolar transistor (DHBT) device employs an InP collector to improve thermal conductivity and reduce the base-emitter junction temperature rise. DHBTs were grown with heavily doped InGaAs or InP sub-collectors for low resistance contacts. As expected, the all-InP collector (sub-collector and collector) had the lowest thermal resistance while the all-InGaAs collector (sub-collector and collector) had the highest thermal resistance. For a device with emitter size of 1 /spl times/ 3 /spl mu/m/sup 2/, the room temperature thermal resistance of the all-InP collector DHBT was 3.9/spl deg/C/mW. The DHBT with an InGaAs sub-collector had a thermal resistance of 5.6/spl deg/C/mW, while the SHBT had a thermal resistance of 12.3/spl deg/C/mW. Also compared were effects of device layout parameters on thermal resistance and the effect of the topside metal thickness. Devices with the largest perimeter-to-area ratio had the lowest thermal resistance when normalized to emitter area. HBTs with conservative alignment tolerances (L1) had similar thermal resistance to those with aggressive alignment tolerances (L2). The reduced parasitic capacitance of the L2-style SHBT improved the device f/sub T/ from 150 to 183 GHz at 6.0-mA collector current. Alternately, the reduced parasitics allowed the SHBT to operate at 150 GHz f/sub T/ at 2.9 mA, reducing the junction temperature rise by more than half. Doubling the topside metal thickness improved the thermal resistance by 31% at room temperature.

44 GHz fully integrated and differential monolithic VCOs with wide tuning range in AlInAs/InGaAs/InP DHBT

A fully integrated and differential AlInAs/InGaAs/InP DHBT voltage controlled oscillator (VCO) with wide tuning range and integrated divide-by-2 static divider was demonstrated for 44 GHz wireless and optical communication applications. To our knowledge, these 44 GHz ICs are the highest frequency fundamental mode fully integrated and differential VCOs with wide tuning range ever reported. The 44 GHz fundamental VCO delivers a typical differential output power of +4 dBm at a center frequency of 44 GHz with a tuning range of up to 4.5 GHz. The measured phase noise shows better than -100 dBc/Hz at 1 MHz offset and better than -80 dBc/Hz at 100 kHz offset. We have achieved more than 6 dB improvement in phase noise performance over the differential SHBT VCO results that we reported last year (A. Kurdoghlian et al., IEEE GaAs IC Symp. Dig., pp. 129-132, 2001).

Investigation Into the Scalability of Selectively Implanted Buried Subcollector (SIBS) for Submicrometer InP DHBTs

Recent attempts to achieve 400 GHz or higher f_T and f _MAX with InP heterojunction bipolar transistors (HBTs) have resulted in aggressive scaling into the deep submicrometer regime. In order to alleviate some of the traditional mesa scaling rules, several groups have explored selectively implanted buried subcollectors (SIBS) as a means to decouple the intrinsic and extrinsic collector design. This allows tau_C to be minimized without incurring a large total C_BC increase, and hence, a net improvement in f_T and f_MAX is achieved. This paper represents the first investigation into the series resistance and capacitance characteristics of submicrometer-width SIBS regions (as narrow as 350 nm) for InP double HBTs. Although the SIBS resistance is higher than that of epitaxially grown layers, the SIBS concept is able to provide good dopant activation and a significant decrease in C_BC. S-parameter measurements are presented to clarify the impact of SIBS geometry variations, caused by both intentional device design and process variations, on f_T and f_MAX. Parasitic resistances and high background doping limit the f_T improvement, but the C_BC reduction is sufficient to demonstrate a 30% increase in f_MAX. Results indicate that further improvements in f_T and f_MAX using the SIBS concept will be possible

Fabrication processes for high performance InAs-based HBTs

InAs-based HBT technology was discussed. Several of the available fabrication processes were presented, as well as the device performance obtained from some of the options.

A numerical analysis to study the effects of process related variations in the extrinsic base design on dc current gain of InAlAs/InGaAs/InP DHBTs

The 2-D simulation program DESSIS was used to simulate InAlAs/InGaAs/InP DHBTs and compare the calculated Gummel plots with measurements from experimental devices employing the same structure. The simulations show that a combination of bulk recombination in the intrinsic device and lateral diffusion of minority carriers to the base contact limit the peak gain of these DHBTs; the lateral diffusion of minority carriers is strongly related to both the lateral and vertical placement of the base contact. For an emitter-edge to base-contact distance, W/sub bl/, as low as 200 nm the lateral diffusion component of the base contact is essentially negligible and peak gain is limited largely by bulk recombination. Conversely, for short W/sub bl/ of 20 nm, which would be typical of self-aligned devices, lateral diffusion is the dominant part of base current and hence, the major factor limiting peak gain. The presence of a residual spacer layer in the extrinsic device is shown to accentuate the gain degradation through enhanced space charge recombination and lateral electron diffusion.