Steven S. Bui

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with f/sub t/>250 GHz and DHBT with f/sub t/>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.

Patterned n+ implant into InP substrate for HBT subcollector

We demonstrate molecular-beam epitaxy (MBE)-grown heterojunction bipolar transistors (HBTs) on InP substrates with a patterned implant n+ subcollector below the epitaxial layers. Device layers grown on implanted/annealed substrates were of similar quality to those on virgin InP. Maximum f/sub t/ and f/sub max/ of 240 and 310 GHz were obtained. We present the process flow, details of the ion implantation, layer characterization, and device results.

Gate-tunable high mobility remote-doped InSb/In1−xAlxSb quantum well heterostructures

Gate-tunable high-mobility InSb/In1−xAlxSb quantum wells (QWs) grown on GaAs substrates are reported. The QW two-dimensional electron gas (2DEG) channel mobility in excess of 200 000 cm2/V s is measured at T = 1.8 K. In asymmetrically remote-doped samples with an HfO2 gate dielectric formed by atomic layer deposition, parallel conduction is eliminated and complete 2DEG channel depletion is reached with minimal hysteresis in gate bias response of the 2DEG electron density. The integer quantum Hall effect with Landau level filling factor down to 1 is observed. A high-transparency non-alloyed Ohmic contact to the 2DEG with contact resistance below 1 Ω·mm is achieved at 1.8 K.

Room-temperature InAlAs∕InGaAs∕InP planar resonant tunneling-coupled transistor

We report an experimental demonstration of room-temperature InAlAs∕InGaAs∕InP planar two-dimensional to two-dimensional resonant tunneling-coupled transistors, in which the tunneling characteristics such as negative differential resistance and peak current are controlled by a surface Schottky gate similar to the state-of-the-art high-electron-mobility transistors (HEMT) with high gain. The tunneling peak voltage was modulated linearly with the Schottky gate voltage with a ratio of nearly unity. Functionality of the device can also be switched between HEMT and tunneling transistor mode. The fabrication process is fully compatible with conventional HEMT processes, offering a fully integrable and scalable tunneling transistor technology.

Single-gate accumulation-mode InGaAs quantum dot with a vertically integrated charge sensor

We report on the fabrication and characterization of a few-electron quantum dot controlled by a single gate electrode. Our device has a double-quantum-well design, in which the doping controls the occupancy of the lower well while the upper well remains empty under the free surface. Electrons tunneling between this accumulation-mode dot and the lower well are detected using a quantum point contact, located slightly offset from the dot gate. Addition spectra starting with N=0 were observed as a function of gate voltage. DC sensitivity to single electrons was determined to be as high as 8.6%.

Investigation Into the Scalability of Selectively Implanted Buried Subcollector (SIBS) for Submicrometer InP DHBTs

Recent attempts to achieve 400 GHz or higher f_T and f _MAX with InP heterojunction bipolar transistors (HBTs) have resulted in aggressive scaling into the deep submicrometer regime. In order to alleviate some of the traditional mesa scaling rules, several groups have explored selectively implanted buried subcollectors (SIBS) as a means to decouple the intrinsic and extrinsic collector design. This allows tau_C to be minimized without incurring a large total C_BC increase, and hence, a net improvement in f_T and f_MAX is achieved. This paper represents the first investigation into the series resistance and capacitance characteristics of submicrometer-width SIBS regions (as narrow as 350 nm) for InP double HBTs. Although the SIBS resistance is higher than that of epitaxially grown layers, the SIBS concept is able to provide good dopant activation and a significant decrease in C_BC. S-parameter measurements are presented to clarify the impact of SIBS geometry variations, caused by both intentional device design and process variations, on f_T and f_MAX. Parasitic resistances and high background doping limit the f_T improvement, but the C_BC reduction is sufficient to demonstrate a 30% increase in f_MAX. Results indicate that further improvements in f_T and f_MAX using the SIBS concept will be possible

HOT MWIR detectors on silicon substrates

The main driving force for High Operating Temperature (HOT) detectors is the strong need for low cost, compact IR imaging solution capable of supporting a wide range of military and civilian applications. In the HOT regime where imagers can be cooled with multi-stage thermoelectric coolers, the major portion of the cost is due to the die-level back-end process, from the chip hybridization to final packaging. We present here an approach to achieve significant cost reduction of MWIR imagers by monolithically integrating III-V devices directly on Silicon substrates for wafer-scale fabrication and packaging of focal plane arrays (FPAs). High quality InAs films can be grown on a blanket Silicon wafer by metal-organic chemical vapor deposition (MOCVD) in a low growth temperature regime that complies with the thermal budget of the Si-electronics. High Resolution Transmission Electron Microscopy reveals predominantly oriented, single-crystal-like InAs films, with Σ3(111) twin boundaries, which our band structure calculations predict to be electrically benign. More intriguingly, selective-area growth on SiO2-masked ROIC-like templates is demonstrated with single-crystal-like InAs film nucleation at small Si(001) openings, together with the suppression of unwanted deposition on the dielectric mask. High crystallinity lateral epitaxial overgrowth of the InAs islands and film coalescence is achieved, enabling the potential to fully cover the entire patterned substrate. MBE-grown MWIR devices (λcut-off = 4.1 μm) on blanket InAs/Si templates exhibit a dark current of 2x10-5 A/cm2 , a specific detectivity of 6x1011 Jones and a quantum efficiency (QE) above 60% at 100K. The QE remains constant at high temperatures (<200K) where the dark current approaches that of baseline single-crystal HOT devices grown on native substrates At 230K, it is 6x10-2 A/cm2, yielding a specific detectivity of 1010 Jones.

Fabrication of InAs/GaSb type-II superlattice LWIR planar photodiodes

We have evaluated selective doping techniques for the fabrication of type II LWIR superlattice planar detectors. Ion-implantation and diffusion of dopants were evaluated for selective doping of the electrical junction region in planar photodiodes. Residual damage remains when superlattice structures are implanted with Te ions with an energy of 190 keV and a dose of 5x1013 cm-2, at room temperature. Controlled Zn diffusion profiles with concentrations from 5x1016 to > 5x1018 cm-3 in the wide bandgap cap layer was achieved through a vapor phase diffusion technique. Planar p-on-n diodes were fabricated using selective Zn diffusion. The I-V characteristics were leaky due to G-R and tunneling in the homojunction devices, for which no attempts were made to optimize the n-type absorber doping level. Work is underway for the implementation of planar diodes with the n-on-p architecture through selective Te diffusion. Due to increased minority carrier lifetimes for p-type InAs/GaSb superlattice absorber layers, planar device with the n-on-p architecture have the potential to provide improved performance as compared to the p-on-n counterparts.

Re-growth of transistors on implanted InP

We have developed a process for the re-growth of InP-DHBTs on selectively implanted subcollectors for the purpose of reducing the base-collector capacitance. Si+ sub-collector implants were performed at >200degC to minimize damage, an important criterion for achieving smooth morphologies in the re-grown devices. Spectroscopic ellipsometry was used to gauge the amount of implant-induced damage in InP. The wafers were annealed in a MOCVD system in a PH3 ambient to activate the implanted Si dopant. DHBT re-growths on wafers processed under the optimal implant, annealing and re-growth conditions exhibited smooth morphologies. For these wafers, the field region of the re-grown transistor was indistinguishable from re-growth in the implanted region, when observed under a Nomarski optical microscope. Using the selective implant and re-growth process we have demonstrated significant reduction of the base collector capacitance in InP DHBTs. The base-collector capacitance was reduced by a factor of two over the standard mesa device with full overlap between heavily doped base and sub-collector regions