Norman K. James

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor

A distributed critical-path timing monitor (CPM) is designed as part of the POWER6trade microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process variation, localized noise and VDD droop, or clock stability. It tracks critical-path delay to within 3 FO2 delays at extreme operating voltages with a standard deviation less than frac12 an FO2 delay. The CPM detects DC VDD droops greater than 10mV and tracks timing changes greater than 1 FO2 delay.

Design of the Power6 Microprocessor

The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.

A 4.6GHz resonant global clock distribution network

A resonant global clock-distribution network operating at 4.6GHz is designed in a 90nm 1.0V CMOS technology. Unique to this approach is the set of on-chip spiral inductors that resonate with the clock capacitance, resulting in 20% recycling of global clock power.

Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor

The POWER6trade is a dual-core microprocessor fabricated in a 65nm SOI process with 10 levels of low-k copper interconnects. Chips with split- and connected-core power supplies are fabricated, modeled, and tested, showing both the advantages and disadvantages of each. On-chip noise measurements are compared to simulation. The noise measurements and simulation both show that the shorted core power grid design has less noise and a higher maximum frequency.

Dynamic measurement of critical-path timing

A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive to 20 mV/bit A/C and 10 mV/bit DC voltage changes, and less than 10degC/bit temperature changes.

A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor

Microprocessor global clock distribution networks use long buffered wires where reflections can be significant. Using accurate transmission-line models and optimization, these reflection effects can be exploited to improve clock-distribution characteristics. The clock distribution network of the P0WER6 microprocessor is designed to run at frequencies exceeding 5GHz using only inverters and transmission lines and is capable of on-the-fly duty-cycle correction

Cycle-domain simulator for phase-locked loops

As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks compared to the processor, it is necessary to use phase-locked loops (PLL) for multiplication and phase aligning of the clocks. A PLL is composed of both digital and analog components and is not modeled well in a design environment for digital systems. There are design tools available that are more adept for doing PLL simulations; however, they can be very costly and are still not suitable for the way PLLs are used in computer systems. The goal of this paper is to introduce a new simulator that is specifically designed for simulating PLLs used in computer systems.

Noise measurements on Power4 Test chip

This paper describes on-chip noise measured on the Power4 Test chip and its impact on the performance of clock and logic circuitry on the chip. It also summarizes the effect of on-module decoupling capacitors on the on-chip noise. The Power4 Test chip was fabricated in 0.1 /spl mu/m effective channel length, 7 metal layer Cu, 1.5 V CMOS silicon-on-insulator technology. The test chip was designed to demonstrate technology feasibility and to facilitate chip and circuit design methodologies for the design of a 1 GHz microprocessor.