Steven R. Dooley

Frequency Tuning Range Extension in LC-VCOs Using Negative-Capacitance Circuits

We present an experimentally validated capacitance cancellation structure to increase the tuning range (TR) of LC voltage-controlled oscillators (VCOs) with minimal phase noise or power impact. The cancellation is based on an ultrawideband differential active negative-capacitance (NC) circuit. An NC scheme suitable for bottom-biased VCOs is analyzed and combined with a CMOS VCO to cancel the fixed capacitance in the LC tank. The NC structure is further modified to be tunable, enabling additional expansion of the VCO TR. By manipulating the quality factor (Q) of the NC tuning varactor pair, a prototype VCO achieves a maximum TR of 27% in a 130-nm technology, while dissipating 13 mA from a 0.9-V supply. The TR is the highest reported at Q-band, covering from 34.5 GHz to 45.4 GHz. Compared to the reference VCO without an NC circuit, the TR is increased by 38%. The measured worst case phase noise is -95 dBc/Hz at 1-MHz offset, and the FOMT is -184.9 dBc/Hz.

Design of Wide Tuning-Range mm-Wave VCOs Using Negative Capacitance

Negative capacitance (NC) circuits of single-ended and differential topologies are presented, analyzed and characterized. The novel NC designs extend the bandwidth of conventional NC circuits while maintaining low power consumption. To compare the performance of the designs, a figure of merit (FOM) is proposed. A power and area efficient NC scheme employing a 130 nm CMOS technology is applied to a mm-wave LC Voltage Controlled Oscillator (LC-VCO) for demonstration. The VCO tuning range is extended by employing the NC circuit to cancel the parasitic capacitance of the LC-tank; resulting in a 35% tuning range increase as compared to the reference LC-VCO circuit. The NC-based LC-VCO achieved a 27% tuning range in the Q-Band, which is the highest reported. Measured results compare closely to the theoretical analysis of the LC-VCO operating from 34.5-45.4 GHz.

AlGaN/GaN HEMT temperature-dependent large-signal model thermal circuit extraction with verification through advanced thermal imaging

Investigation has been done on procedure, development and verification of a large-signal, temperature-dependent model for Aluminum-Gallium-Nitride/Gallium-Nitride (AlGaN-GaN) High-Electron-Mobility Transistors (HEMTs). Procedural issues have been designed to investigate model selection based on application and operation over varying bias. Theoretical and experimental analysis has been completed on device operating point selection in measurement and modeling to account for thermal coefficient extraction and RF dispersion effects. The model has been optimized for use in power amplifier design applications that apply class AB operation. Advanced thermal imaging verification has been performed to validate thermal resistance modeling parameters.

Multiscale 3D thermal analysis of analog ICs: From full-chip to device level

We have developed and employed an automated multi-scale modeling approach to investigate thermal issues in analog integrated circuits (ICs) and to enable ldquothermally awarerdquo design thereof. Thermal analysis from full-chip scale down to the single transistor level was made possible with this approach utilizing the finite volume three-dimensional (3D) numerical technique. We have developed new methods and tools that import GDSII layout of entire IC and generate 3D model. The tool provides a 3D temperature map that can show thermal gradients across a chip, as well as local temperature distribution (hot spots) down to single transistor level. This allows introducing temperature back into design process. Our method and tools are demonstrated on a couple of radio-frequency (RF) chips. The multiscale modeling has been verified with infrared temperature measurements.

In situ study of current-induced thermal expansion in printed conductors using stylus profilometry

An in situ technique that uses a stylus profilometer has been developed for studying current-induced thermal expansion in printed conductive traces and for investigating the effects of expansion on trace resistance and power handling. It was employed to study printed silver traces (50–100 μm linewidths) subjected to a pulsed, millisecond-range current. The traces were aerosol jet printed on a glass substrate using a commercial nanoparticle-based ink. At low peak current densities (J p < 5 × 104 A mm−2), trace expansion is reversible with no permanent resistance increase. At J p ≥ 5 × 104 A mm−2 the expansion becomes irreversible, resulting in reduced power handling and a permanent resistance increase of up to 50%. Since the irreversible expansion decreases density and weakens nanoparticle connectivity, further expansion easily distends the material to the point of forming a void. This is one breakdown mechanism of printed nanoparticle-based silver at high pulsed current.

Considerations in printing conductive traces for high pulsed power applications

The effect of different substrates, inks and sintering methods on the breakdown of a printed conducting trace subjected to a single millisecond-range pulsed current was investigated. The breakdown current density (Jb) of a trace was found to be strongly dependent on substrate thermal diffusivity, which dictates the peak temperature and the cooling rate of the trace. As an example, a 102% increase in average Jb was observed in switching substrate from glass slide to sapphire. Different inks resulted in significant Jb deviation due to their distinct microstructure difference. Traces with dense microstructure exhibited an average Jb that is 42% higher than their porous counterpart. Different sintering methods also resulted in varying Jb. Traces thermally sintered on a hot plate demonstrated an average Jb that is 74% higher than their laser sintered counterpart. Finally, a simple concept that effectively dissipates heat from the trace was explored. It prevented breakdown when the traces were subjected to a single firing pulse used in detonation. Results from this work offer important considerations in printing conductive traces for high pulsed power applications.

A Wide-Band Complementary Digital Driver for Pulse Modulated Single-Ended and Differential S/C Bands Class-E PAs in 130 nm GaAs Technology

Wide-band digital drivers are indispensable for SMPAs (Switched Mode Power Amplifiers) in PWM (Pulse Width Modulation) and PPM (Pulse Position Modulation) applications. This paper presents the design of a wideband RF pre-amplifying buffer, innovated for very low dropout and low power complementary operation in heterojunction technologies affording only depletion type devices. A simple, passive bias level shifting technique is also incorporated to facilitate interfacing the digital modulator in silicon substrate with the PA in III-V wafer. In order to experimentally validate the concepts, the proposed driver is employed for driving an S-band single-ended class-E PA as well as for its differential version, modified to switch over S and C bands, in 130 nm GaAs pHEMT technology. The output powers of the differential amplifier are combined using on-chip transformer balun. Test results of both chips demonstrate that the implemented drivers consume less than 4% of the overall PA efficiencies, wherein the buffer responds linearly to the wideband input pulses when tested alone.

Combined Modeling and Experimental Approach to Improve Mechanical Impact Survivability of GaN Power FET

An alternative approach was taken to improve the high-g shock tolerance of electronic devices. Rather than stiffening electronic devices with potting, the electronic device mass was reduced by an appropriate amount to match the compliance of the device to the circuit board. The devices studied were field effect transistors (FET) in bare die form factor and allowed a wafer thinning process to be utilized. A global-local finite element model was utilized to determine the ideal die thickness for matching the compliance. Test boards were populated with optimal thinned devices and stock devices for comparison on the same board. A three step thinning process was utilized in an effort to minimize the induced defects from the thinning process. The circuit boards with mounted FET’s were dropped from a shock drop tower to successively higher g-shocks up to 60,000-g. The electrical performance of each device was tested and verified after each level of mechanical shock. In general, most devices (both stock and thin) fail electrically before visual evidence of mechanical failure was present. The highest peak acceleration a device survived without failure is used as a figure of merit (e.g. the device failed on the next higher drop). The average of the “peak survived accelerations” for thinned devices is found to be about 25% higher for thin devices than for stock devices. However there was a wide variability in the results, which appears to be the greatest challenge to improving stock tolerance predictability and high confidence reliability of electronic devices.

Damage Characterization for Electronic Components Under Impact Loading

A new experimental method has been develop to characterize critical interfacial damage parameters of solder interconnects subjected to high strain-rate mechanical loading, simulating shock or impact loading. A test apparatus and a test specimen were devised to experimentally characterize such critical damage parameters, particularly interfacial shear strength and fracture toughness. The test fixture was designed to easily mount and unmount test specimens, and accommodate various sizes of electronic components and solder layer thicknesses. Test specimens were fabricated with both metallic and polymeric solder materials, and tests were conducted under various shear load rates. It was found that both strength and fracture toughness exhibit significant rate-dependency.