Larg Weiland

Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits

Manufacturing of integrated circuits relies on the sequence of many hundred process steps. Each of these steps will have more or less variation, which has to be within a,certain limit to guarantee the chips functionality at a target speed. But, not every chip layout is susceptive to process variation the same way, which requires a link between process,capabilities and product design. This paper will present a novel Logic Characterization Vehicle (LCV) to investigate the yield and performance impact of process variation on high volume product chips. The LCV combines and manipulates new or already documented circuits like memory cells and combinatorial logic circuits within a JIG interface that allows fast and easy testability. Beside the functionality of such circuits, also path delay as well as cross talk issues can be determined. A standard digital functional tester can be used, since all timing critical measurements will be performed within the JIG. The described method allows early implementation of existing circuits for future technology nodes (shrinks). A Design Of Experiments (DOE) based implementation of possible layout manipulations will determine their impact on yield and performance of a target design as well as its sensitivity to process variation. The described approach can be used at a much earlier stage of product and process development, which will significantly shorten yield ramp.

Fast extraction of killer defect density and size distribution using a single layer short flow NEST structure

Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size distributions, we present a novel NEST structure. There, many nested serpentine lines will be placed within a single layer only. This mask will be used as a short flow to guarantee a short turn around time for fast process data extraction. Data analysis procedures will provide densities and size distributions of killer defects that will have an impact on product chip yield.

Direct probing characterization vehicle test chip for wafer level exploration of transistor pattern on product chips

Due to recent changes in the manufacturing of FEOL (front end of line) layers it is increasingly difficult to provide rapid learning cycles required to drive yield improvement during new product introduction (NPI). The Direct Probe Characterization Vehicle (DPCV) Test Chip presented here provides direct access to thousands of transistors on a product chip. Only two masks are needed (contact & metal 1) to provide access to the DUTs of the unchanged FEOL layers of a product chip. The DPCV test chip is capable of matching the distribution of product transistor pattern. Measurement data indicate that corrective actions to the design and/or process recipes will reduce the gap between measured product chip transistors and their expected behavior based on SPICE simulations.

Test time reduction methods for yield test structures

Complexity of integrated circuits has led to hundreds of millions of transistors, wiring lines, and layer to layer via connections on every chip. To allow accurate yield evaluation, it is required that process characterization test chips grow in complexity as well which has let to a significant bottleneck in testing them. Wafers that could be tested in less than two hours in a 0.35/spl mu/m technology now require 10 hours and more in a 0.13/spl mu/m technology. This paper will present methods how test structures can be redesigned to better support testing. Based on those we will present modified test algorithms that will significantly reduce the test time by 50% and more, which will accelerate data analysis and increases efficient use of parametric test systems.

Guest Editorial Special Section on the 2012 International Conference on Microelectronic Test Structures

This special section is comprised of six papers which are based on work that was presented at the 2012 International Conference on Microelectronic Test Structures, held in San Diego, CA, USA, March 19-22.