Dennis Ciplickas

A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance

In this paper, we illustrate a methodology for determining the impact of interconnect pattern dependent variation on circuit performance. The methodology helps enable first pass prediction and can handle large layouts using methods which are reasonably compatible with existing CAD tools. We illustrate the relative utility of the methodology using two case studies. Both studies are drawn from industrial relevant problems: unwanted skew in a balanced clock tree and capacitance variation of a critical net in an SRAM array.

Simulating the impact of pattern-dependent poly-CD variation on circuit performance

In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 /spl mu/m 64/spl times/8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell.

Simulating the impact of poly-CD wafer-level and die-level variation on circuit performance

In this paper, we present a methodology for simulating the impact of wafer-level (within-wafer) and die-level (within-die) variation on circuit performance. For a sample 0.25 /spl mu/m 64/spl times/8 SRAM layout, the impact of both die-level and wafer-level poly-CD variation as measured through signal skew and delay is shown to be significant.

Generalization of the photo process window and its application to OPC test pattern design

From the early development phase up to the production phase, test pattern play a key role for microlithography. The requirement for test pattern is to represent the design well and to cover the space of all process conditions, e.g. to investigate the full process window and all other process parameters. This paper shows that the current state-of-the-art test pattern do not address these requirements sufficiently and makes suggestions for a better selection of test pattern. We present a new methodology to analyze an existing layout (e.g. logic library, test pattern or full chip) for critical layout situations which does not need precise process data. We call this method “process space decomposition”, because it is aimed at decomposing the process impact to a layout feature into a sum of single independent contributions, the “dimensions” of the process space. This is a generalization of the classical process window, which examines defocus and exposure dependency of given test pattern, e.g. CD value of dense and isolated lines. In our process space we additionally define the dimensions resist effects, etch effects, mask error and misalignment, which describe the deviation of the printed silicon pattern from its target. We further extend it by the pattern space using a product based layout (library, full chip or synthetic test pattern). The criticality of pattern is defined by their deviation due to aerial image, their sensitivity to the respective dimension or several combinations of these. By exploring the process space for a given design, the method allows to find the most critical patterns independent of specific process parameters. The paper provides examples for different applications of the method: (1) selection of design oriented test pattern for lithography development (2) test pattern reduction in process characterization (3) verification/optimization of printability and performance of post processing procedures (like OPC) (4) creation of a sensitive process monitor.

Predictive yield modeling of VLSIC's

This paper presents a comprehensive methodology for predictive modeling of yield losses in modern VLSI technologies. The in-line defect detection and characterization methods are discussed and a new electrical characterization vehicle (CV) methodology is introduced. A complete chip level yield model that takes into account all the defect mechanisms (random and systematic) is presented. We show that extremely good prediction accuracy is achievable if the micro-level yield models are developed taking into account the available redundancy schemes, and the defect density and size distributions are properly extracted from the inline and CV data. Several examples of practical applications of this comprehensive yield methodology are also given.

Predictive yield modeling for reconfigurable memory circuits

This paper presents a novel approach to the modeling of defect related yield losses in reconfigurable memory circuits. The proposed approach is based on the critical area extracted from the memory layout and the in-line defect inspection data. A complete chip level yield model that takes into account the actual redundancy scheme is presented, with the demonstration of excellent accuracy between the model prediction and bitmap data from an actual flash memory product manufactured by Intel Corporation.

Integrated electrical and SEM-based defect characterization for rapid yield ramp

Challenges of the new nanometer processes have complicated the yield enhancement process. The systematic yield loss component is increasing, due to the complexity and density of the new processes and the designs that are developed for them. High product yields can now only be achieved when process failure rates are on the order of a few parts per billion structures. Traditional yield ramping techniques cannot ramp yields to these levels and new methods are required. This paper presents a new systematic approach to yield loss pareto generation. The approach uses a sophisticated Design-of-Experiments (DOE) approach to characterize systematic and random yield loss mechanisms in the Back End Of the Line (BEOL). Sophisticated Characterization Vehicle (CV)TM test chips, fast electrical test and Automatic Defect Localization (ADL) are critical components of the method. Advanced statistical analysis and visualization of the detected and localized electrical defects provides a comprehensive view of the yield loss mechanisms. In situations where the defects are not visible in a SEM of the structure surface, automated FIB and imaging is used to characterize the defect. The combined approach provides the required resolution to appropriately characterize parts per billion failure rates.

Layout manufacturability analysis using rigorous 3-d topography simulation

This paper presents the latest development of Metropole-3D, a three-dimensional vector simulator that is designed to rigorously simulate the photolithography process in VLSI manufacturing. The development work includes implementation of an efficient and stable solution of Maxwells equation, a rigorous model for post-exposure bake (PEB) and a fast marching module which simulates the development of photoresist. The integration of these features into a rigorous overall simulation approach enables Metropole-3D to meet the demands of simulating DUV and even more advanced lithography process. Simulation of Focus-Exposure Matrix (FEM) conditions shows good matching to experiments in both dense and isolated lines. Process variation analysis using Metropole-3D is demonstrated in a study of undercut and other effects as function of defocus, dose, or other parameters. Finally, line end printability analysis is shown, as an example use of Metropole-3D to study manufacturability of advanced optical proximity correction (OPC).

Processing High Volume Scan Test Results for Yield Learning

Yield of nanometer-scale devices is increasingly challenging due to the increasing contribution of systematic defects that are affected by the product design itself. While inline inspection has been the conventional tool used to detect and isolate significant yield limiting mechanisms, there is a need to augment this information with the analysis of electrical test results obtained using electrical structural test of the final product. The biggest challenge is employing new methods and tools that can accommodate the voluminous amount of data that can accumulate during this process. This paper describes the methods and tools required to manage the data in both time and data-volume efficiency. The described methodology includes the levels of data accumulation and the processing at the various levels; at the tester, offline pre-processing to convert the electrical failures to the specific physical circuit elements causing the fault, and then to the yield management system

Impact of layout at advanced technology nodes on the performance and variation of digital and analog figures of merit

New technologies and integration schemes introduced over the last few generations have increased the sensitivity of transistor performance and variation to its layout and environment. This paper describes an infrastructure for efficient statistical characterization of the transistor variation. The impact of the increased sensitivity of transistor characteristics to its layout and environment is illustrated through a variety of figures of merit for digital, analog and RF design. Examples of layout parameters and their interaction that cause a large variation in these figures of merit illustrate the applications of this infrastructure.