John Kibarian

Analysis of mixed-signal manufacturability with statistical technology CAD (TCAD)

We have developed a methodology which combines technology CAD (TCAD) simulation with statistical analysis of empirical data to predict and control the manufacturability of IC fabrication processes. As a result, manufacturing tolerance or sigma-based models (also known as worst-case models) can be determined before a significant sample size of fabricated devices can be characterized. Early on in the development cycle, empirical data is collected, and models built from simulated data are refined. These revised models are used to determine process control limits, and optimize in-line and electrical test measurement (E-test) for maximum observability of variation. As the process is stabilized, further refined models are used to perform yield diagnosis and tolerance analysis of circuits. This methodology has been applied to a number of BJT and submicrometer CMOS processes to create predictive sigma-based models, modify the fabrication recipe to meet objective specifications as development proceeds, and finally use them to control the manufacturing line.

Simulating the impact of pattern-dependent poly-CD variation on circuit performance

In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 /spl mu/m 64/spl times/8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell.

Simulating the impact of poly-CD wafer-level and die-level variation on circuit performance

In this paper, we present a methodology for simulating the impact of wafer-level (within-wafer) and die-level (within-die) variation on circuit performance. For a sample 0.25 /spl mu/m 64/spl times/8 SRAM layout, the impact of both die-level and wafer-level poly-CD variation as measured through signal skew and delay is shown to be significant.

Design for manufacturability in nanometer era: system implementation and silicon results

A design for manufacturability method to create manufacturable-by-construction designs is presented. Silicon results show significant yield benefit compared to traditional methods.

Analysis of mixed-signal manufacturability with statistical TCAD

We have developed a method which combines TCAD simulation with statistical analysis of empirical data. As a result, we can determine worst case models before a significant sample size of fabricated devices can be characterized. As measured data is collected we use models built from simulated data to analyze measured in-line and e-test data. We determine what is the minimum set of e-test or in-line measurements to control the SPICE model parameters. As a result we can provide predictive worst case models, update them based on fabrication data as development proceeds, and finally use them to control the manufacturing line.

When IC yield missed the target, who is at fault?

Silicon yield once was dominated by contaminants and particulates, making yield a process issue. But with todays electronics supply chain, multiple suspects may be indicted on manufacturability issues. Who is responsible for preventative actions in manufacturability and yield? The AUTHORs, representing a foundry, a fabless company, an IP provider, two EDA vendors, and an IC design team, will discuss the problems and the solutions for achieving manufacturability and yield goals.

Guest Editors' Introduction: DFM Drives Changes in Design Flow

Design for manufacturability (DFM) has thus far been the focus of extensive study in the semiconductor industry. Although deep-submicron processes enable the manufacture of area-efficient, high-performance chips, navigating the nanometer landscape presents enormous manufacturability challenges.