Christopher Hess

Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies

Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described.

Characterization and modeling of MOSFET mismatch of a deep submicron technology

CMOS technology scaling increases the sensitivity of many common circuit blocks to within die variation and local mismatch. Accurate assessment of the impact of mismatch on these circuits requires extremely precise estimates of mismatch. This paper analyzes the inaccuracies that occur in mismatch estimation methods that rely on combining measurements from a different die and wafers. Use of device arrays to overcome this limitation is described. Measurements from device arrays on a 0.13 /spl mu/m CMOS technology suggest that for technologies with good control of device dimensions, 1/sqrt(WL) relationship of mismatch holds over a very large range of device dimensions.

Device Array Scribe Characterization Vehicle Test Chip for Ultra Fast Product Wafer Variability Monitoring

Lower supply voltages and aggressive OPC on 65 nm and below technologies are causing larger variability of critical device parameters like Vt and Id. With ever increasing clock frequencies, more and more performance related yield loss can be observed even for purely digital circuits. To design more robust circuits it is required to characterize device variability within die, within wafer, wafer to wafer as well as lot to lot. Large samples of device measurements are necessary for accurate variability characterization. A novel Characterization Vehicle (CV) has been developed, which achieves an extremely efficient placement of several hundred devices by arranging them underneath the probing pads. Placed next to product chips, those Scribe CV test chips are providing Vtlin, Idlin, Vtsat, Idsat, Gmlin, and Gmsat for more than 25000 devices per 300 mm wafer requiring less than 20 minutes for testing.

Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits

Manufacturing of integrated circuits relies on the sequence of many hundred process steps. Each of these steps will have more or less variation, which has to be within a,certain limit to guarantee the chips functionality at a target speed. But, not every chip layout is susceptive to process variation the same way, which requires a link between process,capabilities and product design. This paper will present a novel Logic Characterization Vehicle (LCV) to investigate the yield and performance impact of process variation on high volume product chips. The LCV combines and manipulates new or already documented circuits like memory cells and combinatorial logic circuits within a JIG interface that allows fast and easy testability. Beside the functionality of such circuits, also path delay as well as cross talk issues can be determined. A standard digital functional tester can be used, since all timing critical measurements will be performed within the JIG. The described method allows early implementation of existing circuits for future technology nodes (shrinks). A Design Of Experiments (DOE) based implementation of possible layout manipulations will determine their impact on yield and performance of a target design as well as its sensitivity to process variation. The described approach can be used at a much earlier stage of product and process development, which will significantly shorten yield ramp.

Extraction of wafer-level defect density distributions to improve yield prediction

Defect density distributions play an important role in process control and yield prediction. To improve yield prediction we present a methodology to extract wafer-level defect density distributions better reflecting such chip-to-chip defect density variations that occur in reality. For that, imaginary wafermaps are generated for a variety of different chip areas to calculate a yield-to-area dependency. Based on these calculations a micro density distribution (MDD) will be determined for each wafer that reflects the degree of defect clustering. The single MDDs per wafer may be summarized to also provide a total defect density distribution per lot or any other sample size. Furthermore, the area needed for defect inspection may be reduced to just a fraction of each wafer which reduces time and costs of data collection and analysis.

Scribe characterization vehicle test chip for ultra fast product wafer yield monitoring

Sub 100nm technology nodes face more wafer to wafer and lot to lot variability. 300mm wafer manufacturing also faces larger within wafer spatial trends. Monitoring those issues on a per layer basis as well as correlating them to the product yield is key for significant yield improvements. A novel characterization vehicle/spl reg/ (CV/spl reg/) has been developed, which is being used in the scribe line of product wafers. The scribe CV test chip achieves an extremely efficient placement of defect sensitive test structures by arranging those in all layers underneath probing pads that are implemented in the top metal layer only. Placed next to product chips all scribe CV test chips on a wafer can be tested in less than 10 minutes per 300mm wafer. Data analysis unveils layer specific defect densities and fail rates, spatial wafer trends, excursion wafers, and more.

Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability

The performance and variability of transistors with nanometer-scale feature sizes is sensitive to their layout style and environment. This paper describes the use of an enhanced MOS array test structure to provide accurate and precise estimates of the impact of layout on transistor characteristics for an advanced 130nm CMOS technology. Enhanced MOS arrays, combined with statistical analysis of the measurements, provide reliable information on the impact of layout on the transistor characteristics. This can then form the basis for technology development, design rule development and modeling.

Fast extraction of killer defect density and size distribution using a single layer short flow NEST structure

Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size distributions, we present a novel NEST structure. There, many nested serpentine lines will be placed within a single layer only. This mask will be used as a short flow to guarantee a short turn around time for fast process data extraction. Data analysis procedures will provide densities and size distributions of killer defects that will have an impact on product chip yield.

High density test structure array for accurate detection and localization of soft fails

To resolve performance yield issues it is required to detect and localize soft fails such as a contact having 500 ohms instead of its nominal 50 ohms. Soft fails can only be detected within very small test structures, which requires an array design to efficiently use the area of test chips. Here we present a novel high density test structure array, which will enable accurate 4 terminal measurements of 1000 or more very small devices under test (DUT) within each array. On average, only 2 selection devices are required per DUT, which will provide outstanding utilization of the test chip area. Experimental results reveal that within this array traditional test structures can be used beyond their intended purpose to detect additional defect types, which opens the door to significant reduction of overall mask and wafer consumption.

Addressable failure site test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation

As technologies scale down, semiconductor manufacturing processes require more and more areas for test structures to ensure accurate yield estimation. This paper presents design guidelines for test structures with addressable failure sites to efficiently utilize a given area. Different types of test structures with three-level interconnects are developed and validated using a novel simulation system. Based on the proposed algorithm, single and multiple defects can be detected and identified precisely without ambiguity. The methodology standardizes the design of test structures for defect capturing as well as their usage within a common pad frame, which can be shared for various processes and applications. A test chip of 22/spl times/6.6 mm/sup 2/ containing a variety of types of these test structures was implemented to demonstrate the design feasibility.