Rakesh Vallishayee

A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance

We present a methodology to study the impact of spatial pattern dependent variation on circuit performance and implement the technique in a CAD framework. We investigate the effects of interconnect CMP and poly CD device variation on interconnect delay and clock skew in both aluminum and copper interconnect technology. Our results indicate that interconnect CMP variation strongly affects interconnect delay, while poly CD variation has a large impact on clock skew in a 1 GHz design. Given this circuit impact, CAD tools in the future must account for such systematic within-die variations.

On the impact of dishing in metal CMP processes on circuit performance

In this paper, we explore the impact of dishing in metal CMP processes on circuit performance. The impact on power distribution networks and clock distribution networks, critical components in modern VLSI designs, is of specific interest. For the two examples given in this paper, we find the impact to be very small.

Impact of layout at advanced technology nodes on the performance and variation of digital and analog figures of merit

New technologies and integration schemes introduced over the last few generations have increased the sensitivity of transistor performance and variation to its layout and environment. This paper describes an infrastructure for efficient statistical characterization of the transistor variation. The impact of the increased sensitivity of transistor characteristics to its layout and environment is illustrated through a variety of figures of merit for digital, analog and RF design. Examples of layout parameters and their interaction that cause a large variation in these figures of merit illustrate the applications of this infrastructure.

IC yield prediction and analysis using semi-empirical yield models and test data

This paper presents the result of an extension to the concept of Micro-Yield modeling. We have developed a design attribute extraction and yield prediction software system that - given the characterization of a semiconductor process via complex test chips that we call Characterization Vehicle test chips and IC product layout and a set of proprietary yield models - computes detailed contributions of different yield models, of geometrical chip regions and of parts of the chip circuitry to the overall chip yield. The organization of the computed output allows easy comparison of predicted yields to inspection and electrical test measurements, where the electrical tests can include failure bit maps for memories and scan tests results for logic circuits. After we review the concept of the Yield Impact Matrix, we define a more general Micro-Event paradigm and introduce the Extended YIMP. We discuss its application to yield loss root-cause analysis, review related work and present example applications of the overall system built around this concepts.

Contact Chains for FinFET Technology Characterization

Electrical characterization remains a key element in technology development and manufacturing of integrated circuits. Contact chain is a well known part of the diagnostic set of test structures used across many generations of silicon processes. Implementation of such test structures becomes challenging in new technologies with 3-D devices, like FinFET. Contacts to active regions of such devices are inherently dependent on the architecture of epitaxial raised source and drain and for proper characterization require the presence of transistor gates, which set the environment for contacts. This paper describes a new type of test structure, so-called gated contact chains, developed for contact process characterization in FinFET technologies. Instead of simple chain of contacts, each structure contains a series of active devices with common gate electrode used to turn on the chain of transistors to enable measurement of chain resistance. To discriminate between chain failures caused by an open contact or by other mechanisms (e.g., bad transistor with very high threshold voltage) a series of measurement under various test conditions was performed and analysed. In order to overcome a limitation of the contact chain size and enable data collection from larger sample of contacts, we proposed to implement the gated chains in addressable arrays, increasing their density and failure rate observability. Finally, the paper presents the examples of electrical failure modes detected by those chains in FinFET process.

Estimating MOSFET Leakage from Low-cost, Low-resolution Fast Parametric Test

A method of estimating the subthershold component of MOSFET off-state current (Ioffs) using low-cost, low-resolution fast parallel parametric test is introduced. This method measures the subthreshold slope and uses it to estimate Ioffs. Measurements of individual transistors show a very good agreement between measured Ioffs and Ioffs estimated using our approach. For a simple pad-efficient transistor array test-structure, where unselected devices can add additional noise to the subthreshold measurements, the sum of extracted Ioffs for all transistors in an array is strongly correlated to the measured array Ioffs, even though it does not match the measured array Ioffs. The strong correlation is used to derive calibration factors which are then used to estimate individual transistor Ioffs from array test structures. This allows statistical characterization of transistor leakage during volume production with minimal test time overhead. The applications of statistical off-state leakage characterization to diagnose IDDQ yield problems during production are also described.

Product relevant device leakage scribe characterization vehicle test chip for efficient full wafer testing

Being successful in semiconductor manufacturing of sub 50nm devices requires controlling variability of device leakage. Full wafer monitoring is essential to provide significant data. The Device Leakage Scribe Characterization Vehicle (CV®) Test Chips presented here fit well within the scribe area constraints of product wafers. Their devices under test (DUT) are using product relevant layout pattern to support new product introduction. Those DUTs are passively connected into a Passive Leakage Array (PLA) to increase the signal to noise ratio of the device leakage measurements, which is essential to enable full wafer testing within existing test time restrictions on product wafers. Furthermore, the PLAs can be arranged inside a Multiplexed Leakage Array (MLA), which significantly increases the number of experiments within the precious scribe line area.