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Dive into the research topics where Brian L. Tessier is active.

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Featured researches published by Brian L. Tessier.


Archive | 2004

Diffused extrinsic base and method for fabrication

Marc W. Cantell; James S. Dunn; David L. Harame; Robb Allen Johnson; Louis D. Lanzerotti; Stephen A. St. Onge; Brian L. Tessier; Ryan W. Wuthrich


Archive | 2002

Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures

Wesley C. Natzle; Marc W. Cantell; Louis D. Lanzerotti; Effendi Leobandung; Brian L. Tessier; Ryan W. Wuthrich


Archive | 2004

MOSFET DEVICE WITH IN-SITU DOPED, RAISED SOURCE AND DRAIN STRUCTURES

Wesley C. Natzle; Marc W. Cantell; Louis D. Lanzarotti; Effendi Leobandung; Brian L. Tessier; Ryan W. Wuthrich


Archive | 2007

STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDE

Huilong Zhu; Siddhartha Panda; Jay W. Strane; Sey-Ping Sun; Brian L. Tessier


Archive | 2008

FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE

Ricky S. Amos; Wesley C. Natzle; Siddhartha Panda; Brian L. Tessier


Archive | 2005

Undercut and residual spacer prevention for dual stressed layers

Huilong Zhu; Brian L. Tessier; Huicai Zhong; Ying Li


Archive | 2010

METHOD OF FORMING A GUARD RING OR CONTACT TO AN SOI SUBSTRATE

Amanda L. Tessier; Bryant C. Colwill; Brian L. Tessier


Archive | 2006

SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVICES OF SAME CONDUCTIVE TYPE ON SAME SUBSTRATE

John C. Arnold; Dureseti Chidambarrao; Ying Li; Rajeev Malik; Shreesh Narasimha; Siddhartha Panda; Brian L. Tessier; Richard S. Wise


Archive | 2005

SELF-ALIGNED DUAL STRESSED LAYERS

Huilong Zhu; Brian L. Tessier; Huicai Zhong


Archive | 2004

A MANUFACTURABLE METHOD AND STRUCTURE FOR DOUBLE SPACER CMOS WITH OPTIMIZED NFET/PFET PERFORMANCE

Sadanand V. Deshpande; Dominic J. Schepis; Brian L. Tessier

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