Sung-Il Chang

Reliability Characteristics of TANOS (TaN/AlO/SiN/Oxide/Si)NAND Flash Memory with Rounded Corner (RC) Structure

Charge trap flash (CTF) memory is one of the most promising technologies for the next generation NAND technology. Among various CTF memories, excellent manufacturability of TaN-Al2O3-Si3N4-SiO2-Si (TANOS) structure has been successfully developed by achieving 32Gb MLC NAND flash using 40nm technology node (Y. Park et al., 2006). 3 dimensional NAND cells such as hemispherical corner (HC) (D. Kwak et al., 2007) and FinFET TANOS (S. Lee et al., 2006) devices with suppressed short-channel effects and improved data retention characteristic were also proposed as cell structures for the next generation beyond 40nm technology node. However, understanding of other device characteristics such as disturb characteristics of the structures is still insufficient. In this paper, various device characteristics of rounded corner (RC) TANOS including disturb and data retention characteristics are investigated and compared with the conventional planar TANOS. Finally, the rendering of RC TANOS for improving disturb characteristics was proposed.

New phenomena for the Lifetime Prediction of TANOS-based Charge Trap NAND Flash Memory

Through the evaluation and analysis of the data retention characteristics, it was found that the CTF memory cell behaviors are quite different from conventional that of the FG type flash memory cell in terms of Arrhenius plot of data retention because Ea of the CTF memory cell has a high dependency on the bake temperature and P/E cycles. A proper acceleration test condition is needed to predict the data retention lifetime of the CTF memory, considering the change of Ea in the low temperature region (<125°C).

Hole trap effect on time-dependent-dielectric breakdown (TDDB) of high-voltage peripheral nMOSFETs in flash memory application

In this work, the TDDB mechanism in high-voltage nMOSFETs with high-density of pre-existing defects in the gate oxide is investigated. In contrast to the traditional nMOSFETs with very few defects in the gate oxide, the additional hole trapping through the stress-induced generated defects close to the gate side not only induce longer fail time, but also induce smaller voltage acceleration factor and lower 10-year Vmax.

A comprehensive study of degradation behavior of select transistors in the Charge Trap Flash memories

The local electron trapping in the select transistors used in the Charge Trap Flash (CTF) NAND was analyzed in depth for the first time in terms of operation conditions and gate spacer process. In this work, we examined the mechanism of swing degradation in the select transistors with TANOS (TaN-Al2O3-Si3N4-SiO2-Si) structure due to repetitive program/erase [P/E] operation. The swing degradation can be explained by the local electron trapping induced from electric field between select transistors and neighboring transistors. The local electron trapping in select transistors are well correlated to the saturation of threshold voltage in the erased cells. The erase Vth saturation appears to be caused by unfavorable backward tunneling of electrons from gate to the trap layer. The degradation in the select transistor is perfectly solved by decreasing the electric field during erase operation and keeping an appropriate distance between select transistors and neighboring transistors.