R. Daily

3D stacking induced mechanical stress effects

In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65 nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized using finite element modeling and micro-Raman spectroscopy measurements.

Interposer technology for high band width interconnect applications

Silicon Interposer provides very high density interconnect combining through Silicon vias and fine wiring. The concept reported in this paper is implementing integrated power supply layers with decoupling metal insulator metal decoupling capacitor to enhance signal integrity. In addition an upscale damascene process was used to fabricate high density and high bandwidth routing interconnect. A detailed characterization of the warpage behavior along the processing steps and electrical characterization of interposer TSV and BEOL are reported.

Development of underfilling and thermo-compression bonding processes for stacking multi-layer 3D ICs

Assembling multi-layer thinned Si chips to form 3D ICs in a fast, reliable, and cost-effective manner is one of the key processes to enable wider application and commercialization of 3D integration. In this paper the essential aspects of process development for stacking multi-layer 3D ICs are investigated. Combining thermo-compression bonding (TCB) process and the usage of pre-applied wafer-level underfill (WLUF) can significantly reduce the process complexity and time. A novel vertical collective bonding method is proposed and experimentally implemented, showing great potential in process improvement and throughput increase. Based on these techniques, stacking of multiple layers of 50 μm thick chips on bottom dies is successfully demonstrated. Daisy chains consisted of TSVs 5 μm in diameter and 20 μm pitch micro joints, in both bump-to-bump (Sn-to-Cu) and TSV-to-bump (Cu-to-Cu) bonding schemes, are connected with good electrical yield between all the stacked layers.

Process development to enable 3D IC multi-tier die bond for 20μM pitch and beyond

We demonstrate for the first time 3D multi-tier (N=4) 50μm thin die bonding for 3D IC technology using low bonding temperature and pressure for Cu TSVs bonded on Cu bumps with a cost effective structure. Die-to-die (D2D) thermal compression bonding (TCB) process with scrubbing is carefully studied in order to improve the bump height TTV and surface roughness. The bonding temperature and pressure can also be reduced significantly to below 220C and 100MPa. The standalone thin die warpage initially 15μm is reduced to 5.4μm by applying the optimized TCB process. The electrical characterizations show good daisy chain connections between each stacked chip and the resistances are very close to the theoretical values. The cross section SEM proofs good TSV alignment to Cu bump, and TSV nails deform and land nicely onto the Cu bump. Finally, we propose to move forward to die-to-wafer approach and migrate to 10μm bump pitch for advanced package application.

Effects of packaging on mechanical stress in 3D-ICs

In this work the mechanical stress induced in 3D stacks by different packaging process steps is studied. The 3D stacks used in this work are assembled using two identical dies containing a number of stress sensors which are designed and manufactured in 65nm technology. It is observed that the contribution of the package substrate and the die-attach process to the redistribution of mechanical stress inside the 3D stacked IC is more significant than the one of the EMC and that the influence of packaging on the shape and amplitude of local stress around the inter-die interconnects (micro-bumps) is not significant. These observations are supported by the measurements of stress done using micro-Raman spectroscopy and are correlated with the results of finite element modeling and with optical warpage measurements of different packaging configurations.

Wafer applied and no flow underfill screening for 3D stacks

As the demand for 3D packaging increases, selecting reliable and cost effective materials to be used to build these complex packages has gained a lot of importance. As current IC technology nodes are becoming “Moore-than-Moore” challenging, thus industry and research institutes alike are trying to find ways of addressing this challenge. The integration of new types of underfill materials in 3D stacking is one very important part of the package material set that will determine its reliability and cost effectiveness. With the introduction of 3D technology, bump sizes and pitches have been scaled down significantly which in turn has also shrank underfill gaps between dies which complicates the assembly of 3D stacks. The need of new underfill materials and underfilling concepts becomes inevitable. It is quite difficult to make traditional capillary type underfills and underfilling methods to work due to the very narrow gaps and fine bump pitches that 3D stacks have. Pre-applied underfills (Wafer Applied or No Flow) with or without fillers (submicron or Nano-fillers) may prove to be a suitable solution for this concern. Using a 2 die-stack test vehicle with a bump pitch of 40 μm (with Cu and Cu/Sn bumps) and an underfill gap of 13.5 μm, four (4) different underfill materials (2 NUFs and 2 WAUFs) were screened. This paper will report on the assessment done for both wafer applied and no flow underfill materials, the differences in the application process, the materials filling and stacking process capabilities and finally the reliability of the 3D stacks. The materials were initially screened based on the test vehicle geometry then processed thru the different phases of the screening process. The changes in thermo-compression bonding parameters used in the experiment to improve the electrical yields will also be discussed. It will also be shown how underfill materials with and without fillers differ in the thermo-compression bonding force required to be able to get good bump-to-bump connection.

Experimental thermal characterization and thermal model validation of 3D packages using a programmable thermal test chip

In this paper, we present the experimental characterization of 3D packages using a dedicated stackable test chip. An advanced CMOS test chip with programmable power distribution has been designed, fabricated, stacked and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling, and soldered to the PCB. Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, thermal finite element and compact models are experimentally validated using a dedicated power map with multiple heat sources. Finally, the 3D test package is used to emulate the thermal behavior of a packaged memory-on-logic stack and to assess the thermal interaction between the chips.

Wafer reconstruction: An alternative 3D integration process flow

Wafer reconstruction is a process of forming an integral handle-able wafer by filling the gaps between the dies after die-to-wafer assembly to allow for further processing on the landing wafer, e.g. thinning, redistribution layer deposition, and bumping. This paper examines key aspects and challenges of different wafer reconstruction process flows. Based on analytical and finite element method modeling, guidelines for material selection and structural design are generated. One selected process flow is successfully demonstrated in a typical 300 mm eWLB production environment, proving the feasibility of wafer reconstruction as a 3D integration process flow.

Developing underfill process in screening of no-flow underfill and wafer-applied underfill materials for 3D stacking

The demands and challenges in pushing the limits of Moores Law made the 3D IC stacking radiate the pressure for MPTs (materials, processes and tools) in keeping up with the technology. The 3D IC architecture design built around the TSVs, micro-bumps and thinned wafers/dies is the center of the show, of which the MPTs must conform and be viable to be part of the supporting cast. Underfillings main objectives is to provide the mechanical stability for micro-bumps and prevents moisture between the resulting gap between dies before the 3D stack is sent for packaging. With several complexities in 3D stacking had to be considered and addressed in applying the underfill materials. Complexities such as the stacking options Die-to-Die (D2D) or Die-to-Wafer (D2W), the thicknesses of the dies to be stacked (~50 um die thickness), the thermo-compression bonding parameters to be used and the behavior of the underfill materials to the different process parameters had to considered during the characterization process of underfills.

Microscrubbing: An alternative method for 3D thermocompression bonding CuCu bumps and high bump density devices with low force, time and temperature

Requirements for thermocompression bonding (TCB) successfully are dependent on the material as well as the area required to join. One of the paths for 3D integration is bonding Cu to Cu bumps or TSVs to bumps. A second path is by integrating fine pitch high density array of bumps, which may equate to >37000 bumps in a 8×8mm die size. Both require a significant amount of pressure as well as temperature before a good bond is achieve. For Cu to Cu bonding, temperatures >300°C is required as well as a compressive force that is needed to overcome the yield point of the metal, causing plastic deformation. On fine pitch high density array of bumps, a massive amount of force is needed to overcome the area of metal to bond. For instance a device with 37000 bumps (40μm pitch) would require at least 121kg of force to successfully bond. In this paper, we take a look on an alternative method of thermocompression bonding where we define, explore and characterize microscrubbing as an added process step during the bond. Experiments comparing differences between the standard TCB and the alternative method will also be explained. The experiment set involves die to die (D2D) stacking and is also applicable to D2W stacking. Experiments are done considering units with underfill using no-flow types. We discuss key understanding on the significant difference and improvements which microscrubbing contributes to the whole bonding process. It also touches on possible effects to bond quality and underfill reactions. In summary this paper covers tool parameters and material behavior during the thermocompression stacking process, exploring microscrubbing as an alternative method to direct TCB. The goal of the paper is to facilitate fundamental learnings and improvements on 3D stacking as a whole by exploring alternative methods.