L. J. Tang

Size difference in dielectric-breakdown-induced epitaxy in narrow n- and p-metal oxide semiconductor field effect transistors

The physical dimension of the hillocks formed during gate-dielectric-breakdown-induced epitaxy (DBIE) is found to be dependent on transistor type. When narrow transistors of area between 3.0×10−10 and 8.0×10−10 cm2 with a gate oxide ranging from 16 to 33 A electrically stressed in inversion mode under the same accelerated stress condition, the DBIEs formed in the n-metal oxide semiconductor field effect transistor (MOSFET) are found to be always about 2 times or more larger than that in the p-MOSFET. The difference in the DBIE dimensions is primarily attributed to a larger percolation leakage current in the n-MOSFET during the gate oxide breakdown transient.

Fundamental narrow MOSFET gate dielectric breakdown behaviors and their impacts on device performance

The post-breakdown (BD) degradation of ultrathin gate oxide Si MOSFET devices is studied by electrical characterization, cross-sectional transmission electron microscopy (TEM) analysis, and theoretical simulation. It is shown that MOSFET devices can remain functional even if a physically direct short between the gate electrode and Si substrate is established. On the other hand, a device can suffer from total failure while no physical damages can be observed under TEM. The physical location of the BD point is shown to be of critical importance in determining the type of BD and the post-BD electrical characteristics of the device. The ability to precisely categorize the gate oxide BD modes in narrow MOSFETs enables us to reevaluate the impact of the gate dielectric BD on the post-BD device performance, and its influence at the circuit levels.

Nickel-Silicided Schottky Junction CMOS Transistors With Gate-All-Around Nanowire Channels

We demonstrate high-performance Schottky CMOS transistors with NiSi source/drain and gate-all-around (GAA) silicon nanowire (~5 nm) channels. The transistors exhibit good I on/I off characteristics, along with fully controlled shortchannel effects revealed by low drain-induced barrier lowering (~10 mV/V) and near-ideal subthreshold swing (~60 mV/dec). Although the N-MOSFET required dopant segregation to suppress the ambipolar behavior, excellent P-MOSFET characteristics could be achieved without the use of barrier modification techniques. We attribute this to the Schottky barrier thinning in a nanosized metal-semiconductor junction and superior gate electrostatic control in a GAA nanowire architecture.

Structure of the oxide damage under progressive breakdown

Abstract The I–V characteristics of ultra-thin gate oxides under progressive breakdown (BD) show a common behavior, indicative of well-defined general physical features of the BD spot. Transmission electron microscopy (TEM) observations give some hints about this structure and on this basis we propose a physical model of the post-BD current, which is in good agreement with data.

Structure and Conductance of the Breakdown Spot During the Early Stages of Progressive Breakdown

It has been shown that under accelerated stress below ap4 V, thin gate oxides are subject to progressive breakdown (BD), i.e., a gradual growth of the BD spot up to a destructive BD. This paper investigates the conduction mechanisms of the BD spot during the early stages of progressive BD through the measurement of the I-V characteristics using carrier separation. It is shown that a model with no free parameter based on the concept of cotunneling provides a good evaluation of the post-BD current. This model implies a physical microstructure, and its plausibility is compared to direct transmission electron microscopy (TEM) observations

Improved electrical performance of erbium silicide Schottky diodes formed by Pre-RTA amorphization of Si

Erbium silicide Schottky diodes formed on Si(001) substrate using rapid thermal annealing method show degraded Schottky-barrier height /spl phi//sub Beff/ and ideality factor n due to the presence of silicide-induced microstructural defects which are likely sources of trap states. A method to improve the /spl phi//sub Beff/ and n of the diodes utilizing in situ Ar plasma cleaning to induce a light amorphization of the Si(001) substrate is proposed. Even though the diodes formed in this way are less textured and have a poorer interface, they are free of silicide-induced microstructural defects, leading to an overall improvement in current transport and conduction properties which can be modeled using inhomogenous Schottky contact model.

Gate dielectric breakdown induced microstructural damages in MOSFETs

Numerous failure mechanisms associated with hard breakdowns (HBD) in ultrathin gate oxides were physically studied by high resolution TEM. Migration of silicide from silicided gate and source/drain regions, abnormal growth of dielectric-breakdown-induce-Si epitaxy (DBIE), poly-Si gate melt-down and recrystallization, severe damage in Si substrate and total epitaxy of poly-Si gate and Si substrate of the entire transistor are among the common microstructural damages observed in MOSFETs after hard breakdowns in gate oxides (Gox) were observed electrically. The type of catastrophic failures and its degree of damage are found to be strongly dependent on the allowable current density and total resistance of the breakdown path during the breakdown transient. The physical analysis data from TEM analysis allow us to establish the sequence of the physical damages associated with the Gox HBD in transistors. The proposed model is able to predict the next possible microstructural damage induced by HBD.

Multiple-pulse laser thermal annealing for the formation of Co-silicided junction

Formation of Co-silicide contact layers on narrow silicon regions using multiple-pulse excimer laser annealing is demonstrated. Excellent performance of junction leakage behavior can be attained on narrow-width n/sup +//p and p/sup +//n junction as compared with standard rapid thermal annealed samples. Liquid-phase epitaxial Co-silicide regrowth has been found to occur and create a smooth and abrupt silicide/Si interface with high junction integrity using multiple-pulse laser annealing. Heat confinement created by the shallow trench isolation surrounding the narrow-width n/sup +//p and p/sup +//n junctions has minimized rapid quenching that might result in an amorphous structure. This has facilitated the crystallization of Co-silicide with multiple-pulse laser annealing.

Role of low temperature rapid thermal annealing in post-laser-annealed p-channel metal-oxide-semiconductor field effect transistor

In this letter, the authors study the importance of a low temperature anneal in the removal of crystalline defects resulting from pulsed laser annealing of preamorphized ultrashallow p+∕n junction. Using an additional low thermal budget rapid thermal annealing at 600°C for 60s, suppression of junction leakage current of two orders in a single-pulse laser annealing and one order in a ten-pulse laser annealing is achieved through a reduction of the residual crystalline defects that could not be annihilated by laser annealing. p-channel metal-oxide-semiconductor field effect transistors with good electrical characteristics can be obtained using pulsed laser annealing followed by a low thermal budget rapid thermal annealing.

Pulsed laser-induced silicidation on TiN-capped Co∕Si bilayers

This paper studies the effects of pulsed laser-induced annealing of TiN-capped Co∕Si bilayers with and without preamorphized Si substrate. For a low fluence of 0.2J∕cm2, nonstoichiometry Co silicide with triple-layered structure is formed. On the other hand, highly textured CoSi2 grains in (111) direction are formed for a high fluence of 0.7J∕cm2. The highly textured CoSi2 layer is monocrystalline and fully coherent with the (111) plane of the Si substrate. However, it has a large amount of microstructural defects throughout the layer. Competitive growth mechanisms between crystallization of homogenous intermixed layer and the nucleation from the melt boundary are discussed.