D.-R. Yost

3D via etch development for 3D circuit integration in FDSOI

This paper describes the development of the 3D via etch process.The oxide via etch was developed in a Trikon Technologies low pressure, high density, helicon-based cluster tool. A response surface design-of-experiments (DOE) was performed varying etch pressure and wafer bias to examine their effect on etch profile and etch rates. An anisotropic etch is essential for high packing density. There was an excellent fit between the data and the model. Low pressure and high bias were required to give vertical profiles. Higher etch pressure caused excessive polymer deposition resulting in etch stop. Low wafer bias could not remove the deposited polymer fast enough, also resulting in etch stop.

Effects of Through-BOX Vias on SOI MOSFETs

The metal-filled vias through the buried oxide are integrated with silicon-on-insulator (SOI) MOSFETs. The FET temperature, measured directly using integrated junction diodes, can be lowered by as much as 25degC with these vias. In addition to enhanced DC characteristics, lowered gate resistance and output conductance further improve the RF performance and the extent of improvement is dependent on the FET design.

Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers

United States. Defense Advanced Research Projects Agency (Air Force Contract FA8721-05-C-0002)

Thermal Effects of Three Dimensional Integrated Circuit Stacks

Thermal effects on different tiers of wafer-scale three dimensional (3D) integrated circuits were examined. The temperature was measured using pn diodes, and the heating effects on the characteristics of MOSFETs were compared. It is found that the circuit at the top of the 3D stack is the hottest. Adding metal plugs through the buried oxide or placing metal heat sink at the top surface improves heat dissipation.

Scaling Three-Dimensional SOI Integrated-Circuit Technology

In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide bond strength and demonstration of +/--0.5 mum wafer-to-wafer alignment accuracy. We have established design rules for our 3DIC technology, have quantified process factors limiting our design-rule 3D via pitch, and have demonstrated next generation 3D vias with a 2x size reduction, stacked 3D vias, a back-metal interconnect process to reduce 2D circuit exclusion zones, and buried oxide (BOX) vias to allow both electrical and thermal substrate connections. All of these improvements will allow us to continue to reduce minimum 3D via pitch and reduce 2D layout limitations, making our 3DIC technology more attractive to a broader range of applications.

Channel engineering of SOI MOSFETs for RF applications

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has no body and drain-extension implants.

SOI-enabled three-dimensional integrated-circuit technology

We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ∼40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a 40% size reduction to 1.0 µm and with an associated exclusion zone reduced by a factor of 2, substantially smaller than in bulk-Si 3D through-silicon-via (TSV) approaches. These significant enhancements were demonstrated with our 3D technology based on conventional SOI wafers.

Characterization of a three-dimensional SOI integrated-circuit technology

This paper describe the process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.

Fully Depleted SOI RF Switch with Dynamic Biasing

RF switches based on fully depleted (FD) SOI technology are reported for the first time. In a novel biasing circuit, the conventional bias resistor at the gate of the series MOSFET switch is replaced with another FET, which functions as a variable resistor and presents different resistance optimal for the on-and off-state. The low parasitic capacitance of FDSOI improved the switch performance and the dynamic biasing further increased the saturated power. At 5 GHz, a single-pole double-throw (SPDT) switch with integrated control circuits has 0.75-dB of insertion loss and 39-dB of isolation. The 1-dB-compression power of this dynamically biased SPDT switch approaches 2 W at 5 GHz.

Improvement of SOI MOSFET RF Performance by Implant Optimization

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased by eliminating channel and drain extension implants. As a result, the fmax of the modified n-MOSFET with a 150 nm gate length exceeds 120 GHz, showing a 20% improvement over the standard MOSFET for digital circuits on the same wafer.