J.A. Burns

A wafer-scale 3-D circuit integration technology

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl times/7.5 /spl mu/m 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm/sup 2/ and pixel responsivity of /spl sim/9 /spl mu/V/e at room temperature.

Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip

Shows the feasibility of stacking SOI circuits to build 3D-ICs with dense vertical interconnects; the results are being applied to develop higher performance systems. Low-power circuits with three metal levels are fabricated with a 0.25/spl mu/m fully-depleted SOI technology. Three or more circuit layers are stacked and connected with 3D vias whose size, pitch, and resistance will be decreased by replacing the adhesive process with low temperature oxide bonding and utilizing tungsten plugs to fill high-aspect-ratio vias.

Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFETs

A proposed breakdown model includes the effects of floating substrate and finite silicon thickness. The calculated I-V characteristics in the breakdown region agree well with the experimental results. The results show that (1) the drain-source breakdown voltage of silicon-on-insulator (SOI) n-MOSFETs increases with increasing channel length, increasing positive substrate voltage, and decreasing silicon film thickness; and (2) SOI n-MOSFETs have higher breakdown voltage than their bulk-silicon counterparts at large gate bias, but lower breakdown voltage at small gate bias. >

Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers

A 64times64 laser-radar (ladar) detector array with 50mum pixel size measures the arrival times of single photons using Geiger-mode avalanche photodiodes (APD). A 3-tier structure with active devices on each tier is used with 227 transistors, six 3D vias and an APD in each pixel. A 9b pseudorandom counter in the pixel measures time. Initial imagery shows 2ns time quantization

An SOI-based three-dimensional integrated circuit technology

Three-dimensional integrated circuits (3D-ICs) composed of active circuit layers that are vertically stacked and interconnected are expected to lead to improved logic devices, memories, CPUs, and photosensors (Akasaka, 1986). These circuits require high-density vertical interconnections (3D vias) comparable in aspect ratio to present multilevel vias (Reber and Tielert, 1996). We have constructed and tested 3D ring oscillators and fully parallel 64/spl times/64 active pixel sensors using a 3D assembly technology which utilizes SOI wafers to achieve stacking of multiple circuit layers and unrestricted placement of dense 3D vias.

TSV-Based 3D Integration

Theoretical studies in the 1980s [1, 2] suggested that significant reductions in signal delay and power consumption could be achieved with 3D integrated circuits (3D ICs). A 3D IC is a chip that consists of multiple tiers of thinned-active 2D integrated circuits (2D ICs) that are stacked, bonded, and electrically connected with vertical vias formed through silicon or oxide layers and whose placement within the tiers is discretionary. The term “tier” is used to distinguish the transferred layers of a 3D IC from design and physical layers and is the functional section of a chip or wafer that consists of the active silicon, the interconnect, and, for a silicon-on-oxide (SOI) wafer, the buried oxide (BOX). The basic features of a 3D IC are illustrated in Fig. 2.1 in a symbolic drawing along with a cross-section of an actual 3D IC. The TSV (through silicon via) is an essential feature of the 3D IC technology and is the vertical-electrical connection formed between tiers and through silicon or oxide. A TSV is formed by aligning, defining, and etching a cavity between two tiers to expose an electrode in the lower tier; lining the sidewalls of the cavity with an insulator; and filling the cavity with metal or doped polysilicon to complete the connection. A TSV drawing and a cross-section of a TSV are shown in Fig. 2.2.

Thin silicide development for fully-depleted SOI CMOS technology

Ultrathin silicide with thickness less than 30 nm and specific contact resistivity to silicon less than mid-10/sup -7//spl Omega/-cm/sup 2/ is necessary for achieving low contact resistance in a sub-0.25-/spl mu/m fully-depleted (FD) silicon-on-insulator (SOI) CMOS technology. This contact problem becomes even more severe as one continues to scale down the device dimensions. We first studied the effects of source/drain series resistance and gate sheet resistance on the device speed performance and obtained a set of desired design criteria. These were used along with a transmission line model to yield a silicide design space, which was then used to evaluate the experimental results. Both cobalt and titanium silicide processes were implemented and found to satisfy the design criteria. Final device characteristics were also measured. Several process integration issues related to contact dielectric deposition and contact barrier integrity were found to greatly impact the final contact properties. These along with the detailed fabrication process are discussed.

Process considerations in restructurable VLSI for wafer-scale integration

Wafer-scale integration has recently been demonstrated using a technique called Restructurable VLSI. An array of logic cells embedded in programmable interconnect is fabricated on the wafer. All the parts are tested by wafer probing, and links are made or broken with a laser to wire the complete system. One such chip, a digital integrator 24 cm2in area with 25 MHz input data rate, has been successfully programmed. This paper will describe the RVLSI concept and discuss several aspects of wafer fabrication which are unusual in this technology.

Properties of thin oxynitride gate dielectrics produced by thermal nitridation of silicon dioxide

Oxynitride films have been fabricated by annealing thermal SiO2films in dilute NH3. These films are homogeneous and have breakdown fields over 9 MV/cm. Unlike films prepared by nitridation of bare surfaces, the thickness of these films is determined by the starting oxide and is largely insensitive to the anneal time. The conversion of oxide to nitride increases with anneal time and temperature as shown by Auger and etch rate measurements. Oxidation at 1000°C in oxygen yields low growth rates comparable to those reported (1) for direct nitridation of silicon. After irradiation with a megarad of ionizing radiation flatband shifts of less than 0.3 volt for gate bias of 5 volts were measured. This shift is mainly due to mobile charge. Conversion of oxide to oxynitride films should make it possible to fabricate by ordinary processing reproducible submicron FETs with gate insulation thickness of 100 Å to 150 Å having acceptable breakdown voltages.