C. Ortolland

Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors

Since the 90-nm CMOS technology node, the strained nitride capping layer (i.e., the contact etch stop layer, CESL) is used as a stress-engineering booster that enables transistor improvement. This paper presents a complete mechanical simulation work explaining how the CESL transmits its intrinsic stress to the Si channel. First, it is demonstrated that the CESL stress transmission is the outcome of several CESL parts acting separately (direct effect) or in association (indirect effect) without neglecting the corner effects for small transistors. Then, all the different contributions of these CESL parts on the stress transfer way for long and short channels are explained. Finally, some guidelines are given for a n optimization of the usage of CESL

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD=1.0V.

Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology

A novel silicide formation technique using milli-second anneal is reported for the first time, delivering superior silicide film morphology that translates electrically into significant yield improvement over a conventional soak anneal, without any degradation of transistor performances. In addition, we demonstrate how this new technique enables the integration of thin silicides required for further junction scaling, and demonstrate up to 6nm gate length reduction and more than 1 decade junction leakage imporvement.

Nonuniform Mobility-Enhancement Techniques and Their Impact on Device Performance

Nowadays, process-induced stress is the preferential industrial method to enhance circuit performances. One of the most popular techniques is the strain induced by contact etch-stop layer. This technology induces a drain-current enhancement which depends on the device dimensions. This strong behavior has already been reported in the literature. In this paper, we propose a simple semianalytical physical model to understand the origin of this dependence and to highlight the physical limitations of the stress techniques. With this model, after a calibration, it would be possible to predict the MOSFET performance for a given transistor gate length. This approach is validated by experimental data and explains the reduction of the drain-current enhancement that is observed for ultrasmall gate-length MOSFET.

Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented.

Ion-implantation-based low-cost Hk/MG process for CMOS low-power application

This paper demonstrates for the first time a low cost, low complexity process CMOS Hk/MG for low-power applications with Vth controlled by gate Ion-Implantation (I/I) and High-k capping for NMOS and PMOS, respectively. Novel advanced electrical and physical characterizations provide unique insights about the underlying mechanism of Vth adjust induced by I/I into the metal. Improved RO performance, with excellent uniformity and matching characteristics have been achieved without reliability degradation.

Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability

In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lgmin meeting the 32 nm node requirement. In addition, we highlight the implication of the metal gate integration flow (ldquogate-firstrdquo vs. ldquogate-lastrdquo) on the junctions design. Also, we demonstrate that a millisecond anneal only (MSA-only) process can fulfill even the stringent junction leakage requirement for low power applications. Finally, based on a combination of physical and electrical characterization, we show for the very first time that micro-uniformities specific to this diffusion-less process have a negligible electrical impact in nominal devices.

Laser annealed junctions: Pocket profile analysis using an atomistic kinetic Monte Carlo approach

In this study, we report on the device impact related to B pocket diffusion/deactivation using an atomistic kinetic Monte Carlo (KMC) diffusion modeling. An atomistic distribution of B-clusters in nFET channel region is shown. Spike-RTA scaling down to 1000°C for shallow extension formation induces about 10% of B pocket deactivation. KMC reveals that the dominant B-clusters in nFET channel region are BI2, B3I, B3I2 and come from B pocket implants. B-clusters distribute around the tip of the extension and possibly have an influence on Vth variation. Laser annealing (LA) before spike-RTA improves the B pocket effectiveness and can reduce B pocket dose. This fundamental understanding of the LA impact on B pocket clustering enables us to improve the short-channel effect and Vth variation over a Spike-RTA reference.

Strain enhanced low-V T CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.

Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

a imec, Kapeldreef 75, 3001 Heverlee, Belgium b ESAT-INSYS department, Katholieke Universiteit Leuven, 3000 Leuven, Belgium c also Post-doctoral fellow of the Fund for Scientific Research-Flanders (FWO), 1000 Brussels, Belgium d also IWT-Vlaanderen, 1000 Brussels, Belgium e Sony assignee at imec, 3001 Leuven, Belgium f Currently at IBM g Universita della Calabria, Arcavacata di Rende, Italy h Panasonic assignee at imec, 3001 Leuven, Belgium