C. S. Liu

InFO (Wafer Level Integrated Fan-Out) Technology

A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moores Law for the smart mobile as well as internet of things (IoT) applications.

Advanced flip-chip package production solution for 40nm/28nm technology nodes

The key technology challenges and solutions in the packaging and assembly of large dies and/or fine pitch on organic substrates for both the 40 and 28 nm technology nodes are reported. Both eutectic PbSn, Pb-free solders, and Cu pillar bumps were used in the flip chip packages. The key challenge of chip-package-integrations (CPI) due to the use of fragile extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) layer has been resolved by the redesigning of the BEOL structure and optimizing the materials set including both the organic substrate and solder materials, along with process improvements.

Process development to enable 3D IC multi-tier die bond for 20μM pitch and beyond

We demonstrate for the first time 3D multi-tier (N=4) 50μm thin die bonding for 3D IC technology using low bonding temperature and pressure for Cu TSVs bonded on Cu bumps with a cost effective structure. Die-to-die (D2D) thermal compression bonding (TCB) process with scrubbing is carefully studied in order to improve the bump height TTV and surface roughness. The bonding temperature and pressure can also be reduced significantly to below 220C and 100MPa. The standalone thin die warpage initially 15μm is reduced to 5.4μm by applying the optimized TCB process. The electrical characterizations show good daisy chain connections between each stacked chip and the resistances are very close to the theoretical values. The cross section SEM proofs good TSV alignment to Cu bump, and TSV nails deform and land nicely onto the Cu bump. Finally, we propose to move forward to die-to-wafer approach and migrate to 10μm bump pitch for advanced package application.

High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology

High performance passive devices for millimeter wave (MMW) system, including inductor, ring resonator, power combiner, coupler, balun, transmission line, and antenna, are first realized using integrated fan-out (InFO) wafer level packaging technology. The inductors has quality factor over 40; the power combiner, coupler, and balun show lower transmission loss than on-chip passives; antenna has the efficiency of over 60%. These devices on InFO enable low noise and power MMW system for mobile communication and IoT applications.

3D stacking using Cu-Cu direct bonding for 40um pitch and beyond

Most of the challenges for Cu-Cu bonding are bump co-planarity, surface roughness, thermal budget, and interface bonding quality. Normally the process needs high bonding temperature, pressure, and long bonding time. Regarding bump co-planarity, several options are considered, including plating optimization, CMP planarization, fly cut, and bump reflow. In this work we have demonstrated that bump co-planarity and surface roughness are greatly improved by fly cut. The dies with flatten bumps are used to perform Cu-Cu direct bonding via thermal compression bonding (TCB) process. We identify the role and influence of UF (underfill) materials during TCB process. Detailed correlations for TCB parameters and electrical yield are investigated. Cu oxidation layer is found at the interconnect interface and affects stacking yielding. With suitable UF, electrical yield shows improvement up to 100% by optimization of TCB bonding conditions. Cross section SEM (Scanning Electron Microscope) shows the Cu bumps are nicely connected and there is no obvious layer at the interface. Furthermore, fly cut effect is also examined by doing fly cut on top & bottom bumps and fly cut on only top bumps. The result shows that fly cut on both side has higher yielding and lower daisy chain resistance than fly cut only on one side. Finally, we successfully demonstrated that TCB temperature and time could be reduced below 300C and less than 900sec, respectively, with 80% electrical yielding.

Ultra Fine Pitch / Low Cost FCCSP Package and Chip Package Interaction (CPI) for Advanced CMOS Nodes

The advancement of Si and flip chip package technologies are driven by high performance mobile processors with high I/O counts. In Si, the back-end-of-line (BEOL) copper interconnect with extreme low-K (ELK) dielectrics has been used to lower RC latency. While for packages, fine-pitch Cu bump is introduced to meet the high I/O density. Corresponding assembly solutions such as thermal compression bonding (TCB) has been used to meet fine-pitch die bonding accuracy requirement. However, the process cost is high due to tool investment and low throughput. Mass reflow, in contrast, supporting processes in batches, enables low cost fine pitch solution. This paper presents the Chip-Package-Interaction (CPI) and assembly process characterization based on the advanced Si incorporated with (1) 60 um pitch Cu bump-on-trace (CuBOT), (2) thermal reflow, and (3) BOT substrate with one escaped trace between bumps. CPI and assembly challenges including ELK peeling, bump bridging, and Cu trace peeling will be investigated. Effects of bump structure, UBM design, polyimide (PI) opening, and substrates material on ELK stress and assembly yield will be addressed. In addition, wafer probing effects on CuBOT packaging yield and reliability will be discussed. Quick temperature cycle (QTC) test for ELK robustness check is employed to speed up Si and bump structure optimization. Full ELK stacking samples with encapsulation passed reliability qualification under JEDEC test conditions. Bias-HAST is further conducted to confirm the process integrity for fine-pitch substrates. Current carrying capability of fine pitch Cu bump is identified by electron-migration (EM) test as well.

Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology

An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of -53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.

Advanced flip-chip package solution for 28nm Si node and beyond

Next generation flip chip package with <;100um fine bump pitch is developed in a cost effective Bump-on-Trace (BOT) package structure for 28nm Si technology node. This is foreseen to be a mainstream for mobile applications in next generations. The key challenges of this new technology include warpage control of molded underfill (MUF) for <; 4 mils of thin die, packaging yield due to finer pitch of bumping/substrate design and thermal/mechanical effect on chip-package-interaction (CPI) [1-2]. CPI due to the use of fragile extreme low-k (ELK) dielectric material in the back-end-of-line (BEOL) layers has been fully characterized. The well-integrated Si/bump/package processes enable reliable CPI and assembly yield. An aggressive and reliable Si/bump/package design and CPI approaches are also discussed.

CPI challenges in advanced Si technology nodes

The key chip-package-integration (CPI) challenges and solutions in the packaging and assembly of advanced Si technology nodes are reported. The key challenge of CPI due to the use of fragile extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) layer has been resolved by optimizing bump structure and materials set including both the organic substrate and solder materials, along with process improvements for both Pb-free solder and Cu bump in flip chip packages.