G.P. Li

Identification and implication of a perimeter tunneling current component in advanced self-aligned bipolar transistors

The identification of a perimeter tunneling current in the base-emitter junction of advanced double-poly self-aligned bipolar transistors has been verified by measuring based current as a function of temperature, bias voltage, and device perimeter-to-area ratio. The perimeter tunneling current at forward bias is found to be predominantly an excess tunneling that depends on the sidewall oxide interface properties, while that at reverse bias is due to band-to-band tunneling resulting from the emitter and extrinsic base profile overlap. Based on experimental results and an analysis of base-leakage-current trade-offs at forward and reverse bias, a device design concept was developed to enhance device performance and processing yield in scaled bipolar transistors. >

A submicrometer high-performance bipolar technology

The description of a submicrometer self-aligned bipolar technology developed to minimize the device topography and to provide shallow profiles for high-performance (ECL) emitter-coupled logic applications is presented. The technology features 0.8- mu m design rules, planar beakless field oxide, polysilicon-filled deep trench isolation, and the use of rapid thermal annealing (RTA). Conventional ECL circuits with 35-ps gate delays, a novel AC-coupled active-pull-down (API) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz are demonstrated.<<ETX>>

Design considerations of high-performance narrow-emitter bipolar transistors

The control of the lateral diffusion of the extrinsic base is a key issue in the downscaling of high-speed bipolar transistors for achieving the lowest base resistance without altering the shallow impurity profile of the intrinsic region. This letter will present the effects of lateral encroachment of the extrinsic-base dopant on the characteristics of transistors with submicrometer emitter stripe width, measurement of the amount of encroachment, and its relationship to the vertical profile.

Bipolar transistor with self-aligned lateral profile

This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-poly-refractory metal emitter stack to reduce the emitter resistance, a high-performance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications.

On the narrow-emitter effect of advanced shallow-profile bipolar transistors

This paper presents a detailed study on the narrow-emitter effect of advanced shallow-profile bipolar transistors. The physical mechanisms behind both the base current and collector current modifications caused by the lateral encroachment of the extrinsic base are investigated. It is shown that in addition to a reduction in the active device area due to the lateral encroachment of extrinsic base into the intrinsic base area, the emitter polysilicon-single crystal interface (bulk property of the polysilicon emitter) and the junction curvature of the emitter/extrinsic-base intercept (perimeter property) also play important roles in determining the current gain for narrow emitter bipolar transistors. The implications on the device and process design for future scaled-down devices are discussed.

An advanced bipolar transistor with self-aligned ion-planted base and W/poly emitter

The fabrication, device profile, and electrical characteristics of an advanced bipolar transistor with an LDD-like self-aligned lateral profile are discussed. An ion-implanted extrinsic base with a low sheet resistance of 55 Omega /square and a junction depth of 0.35 mu m is obtained using rapid thermal annealing. The extrinsic base and emitter are separated by a temporary submicrometer sidewall spacer, which is subsequently removed to maintain a planar surface during the emitter-active-base formation process. The emitter is contacted by a W-TiN-n/sup +/ polysilicon stack with a sheet resistance of 1 Omega /square. As a result of the planarity of the surface during the profile formation for the active region and the decoupling of the structural process from the thin base process, an active base width of 105 nm is obtained. >

A 27 GHz 20 ps PNP technology

Summary form only given. A high-performance double-poly p-n-p technology, with features allowing it to be easily integrated into a more general complementary bipolar process, is described. These advanced p-n-p transistors have 80-nm-wide ion-implanted bases and optimized emitter and collector dopant profiles and are fabricated on a thin p-type epilaver in order to achieve high collector current driving capability. The devices have a measured cutoff frequency of 27 GHz, making them the fastest silicon p-n-p bipolar transistors reported to date. Experimental results on the device characteristics are presented.<<ETX>>

A 23 ps/2.1 mW ECL gate

Simulated output waveforms at 0.1, 0.3 and, 0.6-pF loading of a design optimized for a 0.3-pF nominal load are shown. An AC-coupled APD ECL (active-pull-down emitter-coupled-logic) gate with significantly improved gate delay in the low-power (1-2 mW) regime is described. Unloaded gate delays of 23 and 35 ps at 2.1 and 1.1-mW/gate power, respectively, were demonstrated in a bipolar technology using a double-poly, self-aligned process with emitter width of 0.8 mu m (mask). The device cross-section is presented along with an SEM (scanning electron microscopy) micrograph of the basic gate used in the ring oscillator.<<ETX>>

A subnanosecond 5-kbit bipolar ECL RAM

The authors describe a subnanosecond 512*10-b bipolar ECL RAM using a 1.2- mu m silicon-filled trench-isolated double-poly self-aligned bipolar technology in conjunction with a novel sense-amplifier reference circuit configuration. A 5-kb RAM with an access time of 0.85 ns at a power dissipation of 2.4 W is realized in a chip area of 3.4*4.4 mm/sup 2/. >

A 1.0-ns 5-kbit ECL RAM

A bipolar 512/spl times/10-bit emitter-coupled logic (ECL) RAM with an access time of 1.0 ns and a power dissipation of 2.4 W, achieving an access-time power/bit product of 0.48 pJ/bit, has been developed. The RAM was fabricated using an advanced bipolar technology featuring poly-base self-alignment, poly-emitter shallow profile, and silicon-filled trench isolation with a minimum mask dimension of 1.2 /spl mu/m. A Schottky-clamped multiemitter cell with a cell size of 760 /spl mu/m/SUP 2/ is obtained as a result of compact cell layout and the use of 1.2-/spl mu/m trench isolation.