Andreas Gehring

Multiple Stress Memorization In Advanced SOI CMOS Technologies

Two distinct stress memorization phenomena in advanced SOI CMOS are reported in this work. Both require a capping layer and anneal, but can be categorized as techniques 1) requiring an amorphized source/drain region and low temperature anneal, and 2) requiring a high temperature anneal, independent of the crystalline state of the Si. Both improve NMOS drive current, and the resulting improvements are additive to >27% NMOS IDSAT improvement. The first phenomenon is previously unreported. It has been identified to be localized in the source/drains, and yields more improvement with multiple offset implantation prior to capping and annealing.

FinFET resistance mitigation through design and process optimization

The intrinsic FinFET device structure can provide an estimated 10–20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Ω-um.

Material choice for optimum stress memorization in SOI CMOS processes

Stress engineering has become the sine qua non of any advanced CMOS technology since the 90nm technology node. In this paper, we focus on the influence of material properties and anneal sequences on the benefit of the stress-memorization technique for SOI CMOS transistors. We distinguish between low- and high-temperature stress memorization. Film hardness, stress level, and the order of anneals are found to play an important and partially very different role for these two improvement mechanisms.

Strain Effects on Quasi-Bound State Tunneling in Advanced SOI CMOS Technologies

We study the influence of uniaxial <110> stress on the gate leakage current in advanced silicon-on-insulator (SOI) CMOS devices. The strain-induced shifts of the conduction band valleys and the valence bands are calculated using linear deformation potential theory. After the evaluation of the band edge profile, using a numerical Schrodinger Poisson (S/P) solver, the leakage current is estimated with the quasi-bound states tunneling formalism in a post processing step. The energy shifts of the primed and unprimed subband ladders due to the applied stress yield a re-population of the subbands. This results in a slight decrease for tensile stress and an increase for compressive stress of the leakage current, respectively. These results are in agreement with experimental studies on n-MOS devices

EFFICIENT CALCULATION OF LIFETIME BASED DIRECT TUNNELING THROUGH STACKED DIELECTRICS

We present the efficient simulation of lifetime based tunneling in CMOS devices through layers of high- κ dielectrics which relies on the precise determination of quasi-bound states (QBS). The QBS are calculated using the perfectly matched layer (PML) method. Introducing a com- plex coordinate stretching allows artifical absorbing layers to be applied at the boundaries. The QBS appear as the eigenval- ues of a linear, non-Hermitian Hamiltonian where the QBS lifetimes are directly related to the imaginary part of the eigenvalues. The PML method turns out to be an elegant, numerically stable, and efficient method to calculate QBS lifetimes for the investigation of direct tunneling through stacked gate dielectrics.