Chuan Hsi Liu

Current conduction of 0.72 nm equivalent-oxide-thickness LaO/HfO2 stacked gate dielectrics

Metal-oxide-semiconductor capacitors (MOSCs) incorporating atomic layer deposited (ALD) LaO/HfO2 stacked gate dielectrics were fabricated, where the equivalent oxide thickness (EOT) of the high-k dielectrics is only 0.72 nm and the gate leakage (Jg) is as low as 6.8×10−2 A/cm2. Based on the analysis of the temperature dependence of the gate leakage current from 300 to 500 K, the main current conduction is found to be Schottky emission or Poole–Frankel emission. Moreover, the barrier height (ΦB) at TaC and HfLaO interface is estimated to be about 1.21 eV, and the trap energy level (Φt) is about 0.51 eV.

Electron detrapping in thin hafnium silicate and nitrided hafnium silicate gate dielectric stacks

The kinetics of zero-field and field-induced detrapping of electrons trapped in HfSixOy and HfSiON after positive bias stress on n+-polycrystalline silicon (polySi) gate of n-type metal-oxide-semiconductor (nMOS) capacitors are experimentally investigated. The self detrapping follows a simple logarithmic relation with time while field-induced detrapping upon reversing the stress voltage obeys a simple first-order exponential decay suggesting mono energetic shallow traps associated with tunnel emission of trapped electrons. Finally, our investigation raises questions about the validity of the widely used distributed capture cross section model of electron traps to explain the threshold voltage instability in MOS devices with hafnium silicate gate stacks.

The influence of Hf-composition on atomic layer deposition HfSiON gated metal-oxide-semiconductor field-effect transistors after channel-hot-carrier stress

Metal–oxide–semiconductor field-effect transistors (MOSFETs) incorporating hafnium-silicate (HfSiON) dielectrics with different compositions have been fabricated and their hot-carrier injection (HCI) reliability has also been investigated. The experimental results reveal that the HCI degradation of atomic layer deposition (ALD) HfSiON gate dielectrics is minimized at Hf : Si = 1 : 3. Moreover, the experimental results also show that the increment of oxide trapped charges (ΔNot) depends on Hf content and is about one order of magnitude larger than that of interface traps (ΔNit) after channel-hot-carrier (CHC) stress. Finally, some important interfacial parameters, including ΔNit, ΔDit, and ΔNot, have also been characterized through the charge pumping (CP) technique.

Analysis of promising copper wire bonding in assembly consideration

Although gold wire proposes the good characteristics such as malleability and stabilization, in the cost consideration to promote the package competition, the copper wire provides the better attraction. Therefore, the assembly houses gradually impress on the copper wire bonding technology desirably replacing the traditional gold wire bonding, especially in high-pin-count package. Besides the cost superiority, the electrical resistivity of copper, 1.7 µΩ-cm, is lower than that of gold, 2.2 µΩ-cm, and aluminum, 2.65 µΩ-cm. Furthermore, the mechanical characteristics of copper, such as Youngs modulus and rigidity modulus (130 GPa and 48 GPa, respectively), are larger than those of gold (78 GPa and 27 GPa, respectively). In copper wire bonding, the wire ball on pad demonstrates the excellent neck intensity and the arc shape of the copper wire is more stable. This superiority in molding process is singularly and significantly noticeable.

Heat stress exposing performance of deep-nano HK/MG nMOSFETs using DPN or PDA treatment

Abstract Decoupled plasma nitridation (DPN) or post-deposition annealing (PDA) process after high-k (HK) deposition to repair the bulk traps or the oxygen vacancy in gate dielectric is an impressive choice to raise up the device performance. Before heat stress, the electrical performance in drive current, channel mobility and subthreshold swing with both treatments was approximate, except the higher annealing atmosphere causing the thicker interfacial layer and reducing the overall related dielectric constant. After temperature stress, the electrical performance for all of the tested devices was slightly deteriorated. The degradation degree for electrical performance with PDA treatment group was the worst case due to NH3 atmosphere forming Si–H bond on the channel surface, which was broken after stress and produced more interface state reflected with the increase of subthreshold swing.

Electrical performance of a-Si:H and poly-Si TFTs with heating stress

The amorphous channel (a-Si:H) TFT-LCD technology dominates the large-area flat panel display (FPD) market, but a-Si:H TFTs propose some adverse characteristics, especially in mobility. Therefore, developing poly-Si TFTs to promote mobility and implement the chip-on-glass (CoG) dream is indeed necessary. Using a green continuous-wave laser on amorphous silicon channel formed as poly-crystallization is a possible way in increasing the mobility value up to 450 cm2/V·sec. However, the electrical characteristics for them face the identical trend with temperature heating is degraded. However, the degradation of a-Si:H TFT is worse than that of poly-Si TFT when the device temperature is raised. In this study, the a-Si:H TFTs and poly-Si TFTs with furnace and green laser anneal were chosen. Comparing the transfer characteristics, subthreshold swing (S.S.), threshold voltage (Vth), ON/OFF ratio, field effect mobility (μFE), interface state density (Nit) with temperature effect, some trends are very interesting. The bulk traps were recovered by pseudo-crystallization with increasing temperature, and the transfer characteristics become better than the initial.

Structural properties of ultra-thin Y 2 O 3 gate dielectrics studied by X-Ray diffraction (XRD) and X-Ray photoelectron spectroscopy (XPS)

Ultra-thin yttrium oxide (Y2O3) films (physical thickness of 7 nm) were deposited on p-Si substrates by RF sputtering for MOS applications. The structural properties of the Y2O3 gate dielectrics were studied after RTA from 650 to 850°C. The crystalline phase and chemical bonding state of the films were characterized by X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS), respectively. According to the XRD patterns, Y2O3 films remain amorphous after 850 °C annealing. Moreover, also confirmed by XPS results, the formation of yttrium silicates (YSiO) was observed after 650°C annealing, and the silicate thickness increases with the annealing temperature. It is suggested that the thickness of the silicate layer YSiO dominates the gate leakage current of the MOS capacitors.

Trend of subthreshold swing with DPN process for 28nm N/PMOSFETs

Although decoupled plasma nitridation (DPN) post high-k dielectric deposition shows the better threshold voltage shift than post deposition anneal (PDA), the non-adequate plasma nitrogen (N) concentration and anneal temperature still can dominate the device performance. Using these two variables to probe the impact of HK deposition integrity and the interface quality between channel and gate dielectric is an undetected and published topic. In the experiment, the lower N-concentration and higher anneal temperature is beneficial to the higher drive current and lower threshold for NMOSFET. However, the PMOSFET prefers the lower anneal temperature as well as lower N-concentration. Additionally, the phenomena for the combination of DPN process and strain engineering causing the non-uniform trend distribution of subthreshold swing with device channel lengths were exposed.

A study to performance of electroplating solder bump in assembly

The electroplating methodology in assembly is better than the stencil printing manufacturing in pre-WLCSP (wafer-level chip-scale packaging), especially in quality. Through eight-step process requiring one photolithographic mask, the pre-WLCSP procedures for the electroplating solder bump technology are able to be completed. Comparing this technology with the electroplating gold bump technology, the cost in the previous is more impressive even though the performance of this technology is little lower than the last. Therefore, in this study, the electroplating solder bump in assembly was probed in detail to analyze the possibility of mass-production.

Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO2 gate dielectrics

We present a detailed investigation on positive-bias temperature stress (PBTS) induced degradation of nitrided hafnium silicate (HfSiON)/SiO2 gate stack in n+-poly crystalline silicon (polySi) gate p-type metal-oxide-semiconductor (pMOS) devices. The measurement results indicate that gate dielectric degradation is a composite effect of electron trapping in as-fabricated as well as newly generated neutral traps, resulting a significant amount of stress-induced leakage current and generation of surface states at the Si/SiO2 interface. Although, a significant amount of interface states are created during PBTS, the threshold voltage (VT) instability of the HfSiON based pMOS devices is primarily caused by electron trapping and detrapping. It is also shown that PBTS creates both acceptor- and donor-like interface traps via different depassivation mechanisms of the Si3 ≡ SiH bonds at the Si/SiO2 interface in pMOS devices. However, the number of donor-like interface traps ΔNitD is significantly greater than that ...