Charles L. A. Cerny

Wet Chemical Digital Etching of GaAs at Room Temperature

A new room temperature wet chemical digital etching technique for GaAs is presented which uses hydrogen peroxide and an acid in a two‐step etching process to remove GaAs in approximately 15 A increments. In the first step, GaAs is oxidized by 30% hydrogen peroxide to form an oxide layer that is diffusion limited to a thickness of 14 to 17 A for time periods from 15 to 120 s. The second step removes this oxide layer with an acid that does not attack unoxidized GaAs. These steps are repeated in succession until the desired etch depth is obtained. Experimental results are presented for this digital etching technique demonstrating the etch rate and process invariability with respect to hydrogen peroxide and acid exposure times.

Miniaturized and Reconfigurable CPW Square-Ring Slot Antenna Loaded With Ferroelectric BST Thin Film Varactors

A novel miniaturized and reconfigurable coplanar waveguide (CPW) square-ring slot antenna is presented in this paper. The miniaturization is achieved via a hybrid approach including ferroelectric varactor loadings, high dielectric constant materials, and tuning stub for impedance matching. For the first time, nine shunt ferroelectric (FE) BST (Ba_(1-x)Sr_xTiO₃) thin film varactors are integrated with the CPW antenna structure achieving both antenna miniaturization and reconfiguration at the same time. The size of the miniaturized antenna is reduced to 0.067λ₀ 0.067λ₀ without ground, and 0.1λ₀ 0.1λ₀ with ground. The resonant frequency of the miniaturized antenna can be reconfigured from 5.3 GHz to 5.8 GHz by applying a DC voltage. Measured E-plane and H-plane co-polarized patterns are presented.

Gate currents in heterostructure field-effect transistors: contribution by “warm” electrons

Abstract The two-dimensional electron gas in a geterostructure field-effect transistor is heated by the drain potential. The elevated electron temperature in turn causes an increased gate current. The highest electron temperature is reached at the drain. However, the gate-to-channel barrier is the highest at the drain, which decreases the electron transfer over the barrier. In this paper we investigate the dependence of the gate current on lattice temperature and drain bias, and show that at high drain and gate biases the largest contribution to the gate current comes from the region where the electron temperature, leading to the electron emission from the channel to the gate, is less than 100°C larger than the lattice temperature.

Charge Storage Effects in Pseudomorphic High Electron Mobility Transistors

We present for the first time results on charging effects in fully fabricated pseudomorphic high electron mobility transistors (PHEMTs), using in-situ photoemission and conduction (PEC) studies. The experiments were performed on GaAs based FETs with strained InGaAs channels. These studies evaluate hole storage in the channel area which modifies the threshold voltage of the field effect transistors (FETs). Deep level transient spectroscopy (DLTS) measurements were performed and the results compared to the data obtain from the photo studies. Understanding of hole storage is of significance in modeling the devices since holes are attracted towards the channel when the device is pinched off.

A Reconfigurable Coplanar Waveguide Bowtie Antenna Using an Integrated Ferroelectric Thin-Film Varactor

A novel printed antenna with a frequency reconfigurable feed network is presented. The antenna consists of a bowtie structure patch radiating element in the inner space of an annulus that is on a nongrounded substrate with a ferroelectric (FE) Barium Strontium Titanate (BST) thin film. The bowtie patch is fed by a coplanar waveguide (CPW) transmission line that also includes a CPW-based BST shunt varactor. Reconfiguration of the compact 8 mm × 8 mm system has been demonstrated by shifting the antenna system’s operating frequency 500 MHz in the 7–9 GHz band by applying a DC voltage bias.

Xs-MET-a reduced complexity fabrication process using complementary heterostructure field effect transistors for analog, low power, space applications

The requirements for space-based integrated circuit applications are defined with an emphasis on being radiation tolerant and low power consuming. Flexible analog signal processors (FASPs) are outlined as a means by which effective circuit designs can be utilized to perform a multitude of tasks. The development of complementary III-V technologies have been proven to meet the demands of the space environment, and have demonstrated the potential for frequency operation beyond 1 GHz using power supply voltages at or below 1.5 Volts. The novel fabrication process known as Xs-MET (pronounced kismet, which uses the Creek letter chi, X, and stands for Complementary Heterostructure Integrated Single Metal Transistor), is introduced as a manufacturing technique to be used in FASP design. The Xs-MET fabrication process is outlined with preliminary device results presented. An example of a FASP circuit design using Xs-MET is provided. Conclusions regarding the utilization of the Xs-MET process for FASPs are outlined with comments focusing on a space-based demonstration.