Ross W. Dettmer

Wet Chemical Digital Etching of GaAs at Room Temperature

A new room temperature wet chemical digital etching technique for GaAs is presented which uses hydrogen peroxide and an acid in a two‐step etching process to remove GaAs in approximately 15 A increments. In the first step, GaAs is oxidized by 30% hydrogen peroxide to form an oxide layer that is diffusion limited to a thickness of 14 to 17 A for time periods from 15 to 120 s. The second step removes this oxide layer with an acid that does not attack unoxidized GaAs. These steps are repeated in succession until the desired etch depth is obtained. Experimental results are presented for this digital etching technique demonstrating the etch rate and process invariability with respect to hydrogen peroxide and acid exposure times.

Gate optimization of AlGaN/GaN HEMTs using WSi, Ir, Pd, and Ni Schottky contacts

High electron mobility transistors (HEMTs) were fabricated from AlGaN/GaN on semi-insulating SiC substrates with WSi, Ir, Pd, and Ni Schottky contacts. The devices had 0.30 /spl mu/m T-gates with a total width of 300 /spl mu/m. Devices with Ir gates had the highest measured Schottky barrier and the best small-signal performance of all gate metal combinations attempted. These devices yielded maximum drain current densities of 1.03 A/mm, peak transconductances of 252 mS/mm, unity current gain cutoff frequencies of 46 GHz, and maximum frequencies of oscillation at 64 GHz. Power measurements of these same devices produced 6.5 W/mm with PAE of 32% at 10 GHz CW when optimizing for power.

Thermal studies on heterostructure bipolar transistors using electroluminescence

We have studied electroluminescence (EL) emission from fully fabricated GaAs based heterostructure bipolar transistors. The EL emission occurs due to minority carrier injection into the base and collector layers. Under normal device operation, i.e. with reverse bias on the collector/base junction, collector emission does not occur since holes are not injected into this layer. In this case, only base emission is observed. When a forward bias is applied to the base/collector junction, EL from both the collector and the base is observed. The spectral characteristics of the two EL signals are different since the bandgap of the heavily p-doped base is smaller than that of the lightly n-doped collector. Since the bandgap depends strongly on temperature, the spectral characteristics are used to determine the heating of the HBT due to power dissipation.

Single-cycle lithography process for both large and sub-half-micron features (Poster Paper)

The definition of sub-half-micron gates for gallium arsenide (GaAs)-based field effect transistors is generally performed by direct write electron beam lithography (EBL). Because of throughput limitations in defining large geometries by EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We report a new hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire metallization/lift-off process sequence. This technique has been successfully applied to metal semiconductor field-effect transistor wafers containing devices with dual 0.25 X 75 micron gates connected to 75 X 75 micron gate pads by 5 X 25 micron interconnects. The yields on these wafers have been very high with transistors averaging cutoff frequency values of 42 GHz and transconductance values of 366 mS/mm. Thus, the gate-layer process has been simplified without loss in yield or device performance. We will discuss the entire EBOL process technology including the multi-layer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, and comparison to the standard gate-layer process.

Experimental verification of RF power sensitivity of ferroelectric varactor shunt switches

Ferroelectric varactors placed in a resonant circuit to study the RF power level dependence. At zero-bias, and low microwave power levels, the high capacitance of the varactor results in the resonance of the shunted transmission line, attenuating the signal At higher power level, the ferroelectric varactor capacitance is reduced by the rf signal, detuning the resonance in the shunted stub, and reduces the attenuation level for the signal. The experimental power transfer curve clearly showed that the RF power dependence of the varactor is detectable.

Xs-MET-a reduced complexity fabrication process using complementary heterostructure field effect transistors for analog, low power, space applications

The requirements for space-based integrated circuit applications are defined with an emphasis on being radiation tolerant and low power consuming. Flexible analog signal processors (FASPs) are outlined as a means by which effective circuit designs can be utilized to perform a multitude of tasks. The development of complementary III-V technologies have been proven to meet the demands of the space environment, and have demonstrated the potential for frequency operation beyond 1 GHz using power supply voltages at or below 1.5 Volts. The novel fabrication process known as Xs-MET (pronounced kismet, which uses the Creek letter chi, X, and stands for Complementary Heterostructure Integrated Single Metal Transistor), is introduced as a manufacturing technique to be used in FASP design. The Xs-MET fabrication process is outlined with preliminary device results presented. An example of a FASP circuit design using Xs-MET is provided. Conclusions regarding the utilization of the Xs-MET process for FASPs are outlined with comments focusing on a space-based demonstration.