James S. Sewell

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors using Sc2O3 as the gate oxide and surface passivation

We demonstrated that Sc2O3 thin films deposited by plasma-assisted molecular-beam epitaxy can be used simultaneously as a gate oxide and as a surface passivation layer on AlGaN/GaN high electron mobility transistors (HEMTs). The maximum drain source current, IDS, reaches a value of over 0.8 A/mm and is ∼40% higher on Sc2O3/AlGaN/GaN transistors relative to conventional HEMTs fabricated on the same wafer. The metal–oxide–semiconductor HEMTs (MOS–HEMTs) threshold voltage is in good agreement with the theoretical value, indicating that Sc2O3 retains a low surface state density on the AlGaN/GaN structures and effectively eliminates the collapse in drain current seen in unpassivated devices. The MOS-HEMTs can be modulated to +6 V of gate voltage. In particular, Sc2O3 is a very promising candidate as a gate dielectric and surface passivant because it is more stable on GaN than is MgO.

Wet Chemical Digital Etching of GaAs at Room Temperature

A new room temperature wet chemical digital etching technique for GaAs is presented which uses hydrogen peroxide and an acid in a two‐step etching process to remove GaAs in approximately 15 A increments. In the first step, GaAs is oxidized by 30% hydrogen peroxide to form an oxide layer that is diffusion limited to a thickness of 14 to 17 A for time periods from 15 to 120 s. The second step removes this oxide layer with an acid that does not attack unoxidized GaAs. These steps are repeated in succession until the desired etch depth is obtained. Experimental results are presented for this digital etching technique demonstrating the etch rate and process invariability with respect to hydrogen peroxide and acid exposure times.

Transient characteristics of GaN-based heterostructure field-effect transistors

DC current-switching and power-switching transients of various GaN-based FET structures are investigated. Two different characteristics are compared, namely, thermal and electronic transients. While the thermal transients are mainly reflected in changes in channel carrier mobility, the electronic transients are dominated by charge instabilities caused by the polar nature of the material. The discussion of the electronic transients focuses, therefore, on instabilities caused by polarization-induced image charges. Three structures are discussed, which are: 1) a conventional AlGaN/GaN heterostructure FET; 2) an InGaN-channel FET; and 3) an AlGaN/GaN double-barrier structure. In structures 2) and 3), field-induced image charges are substituted by doping impurities, eliminating this source of related instability. This is indeed observed.

Properties of Ir-based Ohmic contacts to AlGaN/GaN high electron mobility transistors

Measurement of the electrical characteristics of 250 devices on the same 2 in. diameter wafer shows that Ti/Al/Ir/Au Ohmic contacts on AlGaN/GaN high electron mobility transistors (HEMTs) have lower average specific contact resistance after annealing at 850 °C for 30 s (4.6×10−5 Ω cm2) compared to more standard Ti/Al/Ni/Au contacts (2×10−4 Ω cm2). HEMTs with these Ir-based contacts also show average interdevice isolation currents approximately a factor of 2 lower, higher peak transconductance (134 mS/mm compared to 121 mS/mm), and higher device breakdown voltage (31 V compared to 23 V) than the devices with Ni-based contacts. This Ir-based contact metallurgy looks promising for applications requiring extended thermal stability of the HEMTs.

Automated and calibrated whole wafer etch pit density measurements in GaAs

A technique for automated measurement of whole-wafer etch pit density (EPD) for GaAs wafers is presented. The technique relies on an infrared transmission experiment similar to that used to measure EL2 concentration. A theoretical relationship between transmission and EPD is established, including effects due to pit size. The new automated and old visual-count methods are compared on a 3“, low-pressure, liquid-encapsulated Czochralski wafer; it is established that the automated method has much better repeatability. An [EL2] map of this same wafer is also presented.

Thermal studies on heterostructure bipolar transistors using electroluminescence

We have studied electroluminescence (EL) emission from fully fabricated GaAs based heterostructure bipolar transistors. The EL emission occurs due to minority carrier injection into the base and collector layers. Under normal device operation, i.e. with reverse bias on the collector/base junction, collector emission does not occur since holes are not injected into this layer. In this case, only base emission is observed. When a forward bias is applied to the base/collector junction, EL from both the collector and the base is observed. The spectral characteristics of the two EL signals are different since the bandgap of the heavily p-doped base is smaller than that of the lightly n-doped collector. Since the bandgap depends strongly on temperature, the spectral characteristics are used to determine the heating of the HBT due to power dissipation.

Single-cycle lithography process for both large and sub-half-micron features (Poster Paper)

The definition of sub-half-micron gates for gallium arsenide (GaAs)-based field effect transistors is generally performed by direct write electron beam lithography (EBL). Because of throughput limitations in defining large geometries by EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We report a new hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire metallization/lift-off process sequence. This technique has been successfully applied to metal semiconductor field-effect transistor wafers containing devices with dual 0.25 X 75 micron gates connected to 75 X 75 micron gate pads by 5 X 25 micron interconnects. The yields on these wafers have been very high with transistors averaging cutoff frequency values of 42 GHz and transconductance values of 366 mS/mm. Thus, the gate-layer process has been simplified without loss in yield or device performance. We will discuss the entire EBOL process technology including the multi-layer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, and comparison to the standard gate-layer process.