Christopher A. Bozada

Wet Chemical Digital Etching of GaAs at Room Temperature

A new room temperature wet chemical digital etching technique for GaAs is presented which uses hydrogen peroxide and an acid in a two‐step etching process to remove GaAs in approximately 15 A increments. In the first step, GaAs is oxidized by 30% hydrogen peroxide to form an oxide layer that is diffusion limited to a thickness of 14 to 17 A for time periods from 15 to 120 s. The second step removes this oxide layer with an acid that does not attack unoxidized GaAs. These steps are repeated in succession until the desired etch depth is obtained. Experimental results are presented for this digital etching technique demonstrating the etch rate and process invariability with respect to hydrogen peroxide and acid exposure times.

Citric Acid Etching of GaAs1 − x Sb x , Al0.5Ga0.5Sb , and InAs for Heterostructure Device Fabrication

Citric acid/hydrogen peroxide (C 6 H 8 O 7 :H 2 O 2 ) at volume ratios from 0.2:1 to 20:1 was found to provide selective etching between GaAs 1-x Sb x (x=0.15 to 1.0), Al 0.5 Ga 0.5 Sb, InAs, and various III-V semiconductor materials for use in new GaAs and InP based heterostructure transistors and optoelectronic devices. By choosing different concentration volume ratios of citric acid to hydrogen peroxide (χC 6 H 8 O 7 :1H 2 O 2 ), highly selective as well as uniform (nonselective) etching regions were found to exist in these material systems

Analytical Two-Layer Hall Analysis - Application To Modulation-Doped Field-Effect Transistors

The classical magnetic‐field‐dependent Hall coefficient and conductivity equations are inverted to give the mobilities μ1 and μ2 and carrier concentrations n1 (or p1) and n2 (or p2) in two degenerate bands. The two‐band solution holds for arbitrary magnetic‐field strength as long as quantum effects can be ignored (i.e., kT≳ℏeB/m*), and it is argued that the analysis can also be applied to two separate layers up to reasonable field strengths. The results are used to determine the two‐dimensional electron gas mobility and carrier concentration in a modulation‐doped field‐effect transistor with a highly doped cap layer.

Charge-quantization effects on current-voltage characteristics of AlGaAs/GaAs resonant tunneling diodes with spacer layers

An inflection has been observed in the current‐voltage characteristics of several AlGaAs/GaAs resonant tunneling diodes with spacer layers. We provide evidence linking this inflection, as well as the negative differential resistance, to quasi‐bound energy states localized in the charge accumulation well between the emitter spacer layer and the AlGaAs barrier. There are strong indications that this region acts as the injector of electrons through the quantum well region. We propose a model for the electron transport, and show that the singularities in the current are caused by the quantum well state crossing the accumulation layer quasi‐bound states as the bias is ramped.

Electron density in quantum well diodes

A self‐consistent calculation of the electron density and conduction‐band edge is presented. The time‐independent Schrodinger and Poisson equations are solved simultaneously under a high applied bias for structures with thick, lightly doped spacer layers. It is shown that strongly localized states occur in the well and accumulation regions. These states are capable of trapping a substantial amount of charge, which in turn can drastically change the shape of the band edge, and therefore need to be included in studies of the resonant tunneling problem in which the Coulomb interaction must be accounted for.

Charge Storage Effects in Pseudomorphic High Electron Mobility Transistors

We present for the first time results on charging effects in fully fabricated pseudomorphic high electron mobility transistors (PHEMTs), using in-situ photoemission and conduction (PEC) studies. The experiments were performed on GaAs based FETs with strained InGaAs channels. These studies evaluate hole storage in the channel area which modifies the threshold voltage of the field effect transistors (FETs). Deep level transient spectroscopy (DLTS) measurements were performed and the results compared to the data obtain from the photo studies. Understanding of hole storage is of significance in modeling the devices since holes are attracted towards the channel when the device is pinched off.

Depth measurement of doped semiconductors using the Hall technique

A new method using the Hall technique to determine the change in surface layer thickness of doped semiconductors is presented. An equation to calculate the semiconductor thickness change has been determined by comparing the difference in Hall measured sheet carrier concentration and mobility before and after a change in surface layer thickness. Experiments were conducted using a wet chemical digital etch to remove n-type GaAs surface layers having an incremental etch depth control of approximately 15 A in thickness, and the resulting thickness changes were calculated by the Hall technique and measured with a mechanical profilometer. This Hall measurement technique was able to measure changes in surface layer thickness of less than 100 A, and the accuracy of this new technique compared favorably with mechanical profilometer measurements. The new Hall technique method provides accurate measurements of minute thickness changes, and is more accurate than mechanical profilometers for thickness changes less than 150 A.A new method using the Hall technique to determine the change in surface layer thickness of doped semiconductors is presented. An equation to calculate the semiconductor thickness change has been determined by comparing the difference in Hall measured sheet carrier concentration and mobility before and after a change in surface layer thickness. Experiments were conducted using a wet chemical digital etch to remove n-type GaAs surface layers having an incremental etch depth control of approximately 15 A in thickness, and the resulting thickness changes were calculated by the Hall technique and measured with a mechanical profilometer. This Hall measurement technique was able to measure changes in surface layer thickness of less than 100 A, and the accuracy of this new technique compared favorably with mechanical profilometer measurements. The new Hall technique method provides accurate measurements of minute thickness changes, and is more accurate than mechanical profilometers for thickness changes less tha...

Single-cycle lithography process for both large and sub-half-micron features (Poster Paper)

The definition of sub-half-micron gates for gallium arsenide (GaAs)-based field effect transistors is generally performed by direct write electron beam lithography (EBL). Because of throughput limitations in defining large geometries by EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We report a new hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire metallization/lift-off process sequence. This technique has been successfully applied to metal semiconductor field-effect transistor wafers containing devices with dual 0.25 X 75 micron gates connected to 75 X 75 micron gate pads by 5 X 25 micron interconnects. The yields on these wafers have been very high with transistors averaging cutoff frequency values of 42 GHz and transconductance values of 366 mS/mm. Thus, the gate-layer process has been simplified without loss in yield or device performance. We will discuss the entire EBOL process technology including the multi-layer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, and comparison to the standard gate-layer process.

Characterization of AlAs/GaAs superlattice barriers using electrical barrier height analysis

Electrical barrier height measurements on n+‐GaAs–insulator–n‐GaAs structures with short‐period AlAs/GaAs superlattices forming the insulator show the effective conduction‐band discontinuity (ΔEC) of a superlattice barrier (SLB) to be defined by the lowest superlattice energy state. Five structures with different AlAs and GaAs SLB layer thicknesses are investigated. A SLB with GaAs layers greater than 10 monolayers is found to have a ΔEC defined by Γ‐valley states in the GaAs layers, while a SLB with GaAs and AlAs layers less than 10 monolayers and with thicker AlAs layers than GaAs layers is found to have a ΔEC defined by X‐valley states in the AlAs layers. The SLB with GaAs and AlAs layers less than 10 monolayers and thicker GaAs layers than AlAs layers behaves as a random alloy. Negative differential resistance is observed in the current‐voltage characteristic of the sample whose barrier height is defined by Γ‐valley states in the GaAs layers.