Chee Houe Khong

Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects

Continuous increase in demand for product miniaturization, high package density, high performance and integration of different functional chips has lead to the development of three dimensional packaging technologies. Face-to-face silicon (Si) dies stacking is one of the three dimensional (3D) packaging technologies to form a high density module. In this work, a chip level stacked module was demonstrated for medical application and assessed its package level reliability. The chip level stack module is achieved by stacking two thin dies of different size and thickness together using flip chip technology with micro bump interconnects. Electrical simulations are carried out to obtain RLC parameters of micro bump interconnect and complete interconnection from daughter die to substrate. Mechanical simulations are also carried out to study the stress analysis on micro bumps and CSP bumps in the package and parametric study of stacked module package to study the effect of substrate material, underfill material die thicknesses on package reliability and warpage. Test chips are designed and fabricated with daisy chain test structures to access the reliability of the stack module. Pb-free (SnAg) micro bumps of 40 µm on daughter die wafers and Eutectic SnPb solder CSP bumps of 200 µm height on Mother die wafers are fabricated. Mother die and daughter die bumped wafers were thinned to 300 µm and 60 µm respectively using mechanical backgrinding method. These thin dies are stacked using chip to wafer flip chip bonding and underfill process is established for the micro bump interconnects. The assembled Si die stacked modules are subjected to JEDEC package level reliability tests in terms of temperature cycle test (TC), high temperature storage test (HTS), moisture sensitivity test level 1 (MST L1) and MST L3, and un-biased High accelerated stress test (uHAST) and results are presented.

A novel method to predict die shift during compression molding in embedded wafer level package

The increased functionality of cellular phones and handheld devices requires system level integration. Thus there is a strong demand in cell phone maker to move to embedded micro wafer level packaging (EMWLP). But the major problem encountered is die shift during compression molding. This paper presents a novel method to predict the die shift during wafer level molding process. A series of parametric studies are performed by changing the die thickness, die pitch distance and top mold chaste compression velocity. The effect of thinning down the chip thickness affects the pressure difference and local shear rate on the chip surfaces. The rate of change of epoxy mold compound fluid pressure across the die top surfaces is not constant. The local shear rate is increasing linearly from the centre of the wafer to the outermost die. From the parametric studies, the die shift is inversely proportional to the die thickness for wafer level molding. Such a phenomenon will reduce the lithography alignment error in the next process. This paper also shows that by reducing die pitch distance of a 5 × 5 mm2, 500 µm thick chip, the die shift decreases by a factor of 12%. In addition, the top mold chaste compression velocity contributes to the die shift by as much as 28% when the velocity is reduced by 50% from 100 µm/sec to 50 µm/sec Finally it is observed from experiment result that the die shift is not constant in all directions.

3D interconnection process development and integration with low stress TSV

The 3 D interconnect technology with Thru Silicon Via (TSV) have gained tremendous advancement in recent years. Final adoption of TSV technologies requires a robust and cost competitive TSV processes. Sidewall plated TSV with polymer filling can reduce half of total process steps from TSV copper (Cu) seed deposition to front-via1 expose. TSV plating time can be reduced ~ 60% for sidewall plated TSV with polymer filling. Costly Cu removal process through chemical mechanical polishing (CMP) can be skipped in sidewall plated TSV with polymer filling process. Wafer warpage and bow for sidewall plated TSV with polymer filling were shown to be ~70% and ~94%, respectively lower than solid Cu filled TSV. Thermal-mechanical simulation show 20% and 42% reduction of shear and bending stress respectively in the case of sidewall plated TSV with polymer filling.

Numerical modeling of through silicon via (TSV) stacked module with micro bump interconnect for biomedical device

A two-die stacked silicon module with TSV has been developed in this work. Thermal-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-dimensional plane strain analysis using the global-local technique, based on St. Venants principle, is performed on the diagonal cross-section of the wafer. The thermal-mechanical modeling has shown that the shear stress Sxy at the micro-bump, compressive stress Sy at the interconnection and shear stress Sxy at the TSV are reduced for off-pad via as compared to on-pad via. This is because the CTE mismatch between the micro-bump and TSV is no longer effective when the TSV is offset. Also the work presented that the offset distance of the off-pad via does not have an impact to the compressive stress Sy and shear stress Sxy at the interconnection. There are also no significant changes in the shear stress Sxy at the TSV as the off-pad via moves outward to the die edge. As we knows that the bending stress Sx is a major factor contributing to die cracking due to coefficient of thermal expansion (CTE) mismatch. Our simulation results showed that the bending stress Sx of the top die and bottom die was not affected by increasing the offset distance of the off-pad via even to the die edge. Thus it is an advantage to plate the through-silicon-via away from the micro-bump to avoid stresses complication arises from CTE mismatch.

Process challenges and development of eWLP

Embedded Wafer Level Package (eWLP) is designed and developed. The eWLP consists of one silicon die encapsulated with a mold compound and its size is 12mm × 12mm × 0.2mm. The assembly process of eWLP consists of reconfiguration of the dies on an adhesive tape, followed by molding, thinning and rerouting distribution layer (RDL) process. Finite Element Modeling (FEM) is used to understand the stress distribution in the eWLP and provide design input to the configuration of eWLP. The encapsulated eWLP passed 1000 air-to-air thermal cycles (−40 to 125°C), unbiased Highly Accelerated Stress Test (HAST) and moisture sensitivity level 3 (MSL3) test. In this paper, FEM of eWLP, selection of granular epoxy mold compound (EMC), die shift analysis, and warpage study will be discussed in detail.

Process and reliability assessment of 200μm-thin embedded wafer level packages (EMWLPs)

In this paper, we focus how to overcome process challenges, such as die shift and warpage, and to fabricate thin embedded wafer level packages (EMWLPs) with 200μm-thick eventually. The initial warpage of reconfigured wafer after post mold curing (PMC) was about 1.0 ∼ 1.4mm range. After PMC, the molded wafer was background to 200μm thickness and redistribution layer (RDL) process was conducted on both front- and back-sides of the molded wafer sequentially. However, the warpage increased up to several mm during 1st RDL formation so that multi-RDLs process could not be performed due to the largely warped wafer. In order to overcome the large warpage issue, thick Si wafer was adopted as a carrier and the molded wafer was bonded on the Si carrier before RDL process. The measured warpage values decreased from several mm to about 500μm during RDL process by using the Si carrier and two RDLs were fabricated on both sides of the molded wafer. Consequently, the fabrication of 200μm-thick molded wafer for EMWLPs was successfully achieved. Three reliability tests (MSL3, HAST, and TC) were performed with singulated EMWLP modules and no failure was observed in the results of component level reliability. Furthermore, for in-depth understanding of the effects of MCs and carrier types on the die shift of the reconfigured wafer, the die shift values were measured on the molded wafers made of different MCs and different carriers as well. The experimental results are being compared with computational simulation and this can provide basic guidance of material selection and molding process.

Design and Analysis of 3D Stacked Optoelectronics on Optical Printed Circuit Boards

In this study, a low-cost (with bare chips) and high (optical, electrical, and thermal) performance optoelectronic system with a data rate of 10Gbps is designed and analyzed. This system consists of a rigid printed circuit board (PCB) made of FR4 material with an optical polymer waveguide, a vertical cavity surface emitted laser (VCSEL), a driver chip, a 16:1 serializer, a photo-diode detector, a Trans-Impedance Amplifier (TIA), a 1:16 deserializer, and heat spreaders. The bare VCSEL, driver chip, and serializer chip are stacked with wire bonds and then solder jointed on one end of the optical polymer waveguide on the PCB via Cu posts. Similarly, the bare photo-diode detector, TIA chip, and deserializer chip are stacked with wire bonds and then solder jointed on the other end of the waveguide on the PCB via Cu posts. Because the devices in the 3D stacking system are made with different materials, the stresses due to the thermal expansion mismatch among various parts of the system are determined.

Sub-modeling technique for thermo-mechanical simulation of solder microbumps assembly in 3D chip stacking

The submodeling technique is a powerful analysis tool. The method promotes more accurate analysis and also helps enhance productivity. It has been shown that by using displacement-force cut boundary condition method, it can be made even more versatile. The local stress phenomena of the solder microbump have been solved with this approach to demonstrate the concept. From the simulation model, it is known that the ENIG pad thickness has an effect on the aluminium pad stress in the silicon chip. This is important as the shear stress will damage the pad and circuitry on the chip. Previously this is not reported in other literatures as there is no strain gage available that can measure such a small dimension.

Stress Analysis of Embedded Active Devices in Substrate Cavity for System-On-Package (SOP)

The effect of thinning down the chip thickness, will affect the stress pattern in the chip and causes the chip to deform locally when the thickness of the chip is thinner than a certain critical value. Such a local deformation may cause sharp gradient of residual stress around the solder bumps and thus, various failures. This paper shows that by considering the effect of solder bumps on a 50 mum chip, the stress magnitude increases by almost double. In addition, the normal stress (sigmax) in the 50 mum chip is increased by 94% with increasing coefficient of thermal expansion of the embedded material properties. By moving the same 50 mum chip on top surface along the diagonal and side of the BT substrate, it is observed that the stress in the chip remains unchanged. Finally both the shape of parallelogram and square 50 mum chip have a lower stress magnitude as compared to other shapes.