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Dive into the research topics where Cheng-Hsiung Tsai is active.

Publication


Featured researches published by Cheng-Hsiung Tsai.


international interconnect technology conference | 2011

Low damage etch approach for next generation Cu interconnect

Sunil Kumar Singh; Chung-Ju Lee; Cheng-Hsiung Tsai; T. M. Huang; C. W. Lu; T. J. Tsai; Y. S. Chang; Tien-I Bao; Shau-Lin Shue; Chung-Yi Yu

This research focus on low radical plasma etch (LRPE) process and its impact on highly porous dielectric material (extreme-low-k, ELK, k=2.4). We demonstrate a dual damascene (DD) process flow without k degration by low radical and pore sealing plasma etch. Comparing to tranditional DD etching process, 12% resistance-capacitance (RC) improvement, 15% via resistance reduction and a factor of 3 inter-metal-dielectric (IMD) time dependent dielectic breakdown (TDDB) improvement can be achieved by the proposed approach.


international interconnect technology conference | 2017

Advanced patterning approaches for Cu/Low-k interconnects

Cheng-Hsiung Tsai; Chung-Ju Lee; C. H. Huang; Jay Wu; H. W. Tien; Hsin-Chieh Yao; Y. C. Wang; Shau-Lin Shue; Min Cao

The RC delay, electro migration (EM) and TDDB performance become more challenges to meet device requirement as continuous geometry shrink on BEOL dual damascene interconnects. To overcome these challenges from interconnect patterning point of view, we proposed Cu subtractive RIE as a potential solution for next generation Cu/Low-k interconnects.


international interconnect technology conference | 2015

A flexible top metal structure to improve ultra low-k reliability

K. F. Cheng; C. L. Teng; H. Y. Huang; Hsueh-Chung Chen; C.W. Shih; T. H. Liu; Cheng-Hsiung Tsai; C. W. Lu; Y.H. Wu; Hsiang-Huan Lee; Ming-Han Lee; M. H. Hsieh; B. L. Lin; Shang-Yun Hou; Chung-Ju Lee; Hsin-Hsien Lu; Tien-I Bao; Shau-Lin Shue; Chung-Yi Yu

High stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively reduce the transmitted stresses and, thus, resolve the interfacial delamination issue. Along with an optimized chip-package integration solution, a reliable interconnect structure with good electrical performance, has been successfully demonstrated.


international interconnect technology conference | 2012

A novel LWR reduction approach to enhance reliability performance in ultra-thin barrier/porous low-k (K<2.4) interconnect

C. W. Lu; T. J. Tsai; Y. S. Chang; Cheng-Hsiung Tsai; Sunil Kumar Singh; T. M. Huang; Hsin-Chieh Yao; Chung-Ju Lee; Tien-I Bao; Shau-Lin Shue; Chung-Yi Yu

This study evaluated plasma treatment processes on 193i and EUV photoresist to improve the line width roughness (LWR) performance in porous low-k/ultra-thin barrier Cu interconnect. We successfully demonstrated 20% LWR reduction for 193i PR and 11% for EUV PR. Furthermore, the influence of LWR on reliability was evaluated on 45nm line-width test vehicle. A boost of 10 times Time Dependent Dielectric Breakdown (TDDB) and 2 times Eelectrical Migration (EM) was demonstrated.


international interconnect technology conference | 2012

Uncured ELK as a chemical mechanical planarization stop layer in Cu/XLK interconnect

Y.H. Wu; Ming-Han Lee; Cheng-Hsiung Tsai; Hsiang-Huan Lee; Chung-Ju Lee; Hsin-Hsien Lu; Tien-I Bao; Shau-Lin Shue; Chung-Yi Yu

A novel approach of copper CMP stop layer using uncured extreme low-K was demonstrated to improve the within-wafer Rs uniformity on Cu/extra low-k (XLK) interconnect. This CMP stop layer could be converted into a low dielectric constant film by removing porogen with post CMP treatment, hence its impact on overalls film capacitance is minimized.


Archive | 2015

Spacer Etching Process For Integrated Circuit Design

Ru-Gun Liu; Cheng-Hsiung Tsai; Chung-Ju Lee; Chih-Ming Lai; Chia-Ying Lee; Jyu-Horng Shieh; Ken-Hsien Hsieh; Ming-Feng Shieh; Shau-Lin Shue; Shih-Ming Chang; Tien-I Bao; Tsai-Sheng Gau


Archive | 2015

Self-Aligned Double Spacer Patterning Process

Cheng-Hsiung Tsai; Yung-Hsu Wu; Tsung-Min Huang; Chung-Ju Lee; Tien-I Bao; Shau-Lin Shue


Archive | 2013

Lithography Using High Selectivity Spacers for Pitch Reduction

Yu-Sheng Chang; Chung-Ju Lee; Cheng-Hsiung Tsai; Yung-Hsu Wu; Hsiang-Huan Lee; Hai-Ching Chen; Ming-Feng Shieh; Tien-I Bao; Ru-Gun Liu; Tsai-Sheng Gau; Shau-Lin Shue


Archive | 2015

Method of spacer patterning to form a target integrated circuit pattern

Chieh-Han Wu; Cheng-Hsiung Tsai; Chung-Ju Lee; Ming-Feng Shieh; Ru-Gun Liu; Shau-Lin Shue; Tien-I Bao


Archive | 2014

Semiconductor Integrated Circuit With Nano Gap

Cheng-Hsiung Tsai; Chieh-Han Wu; Chung-Ju Lee; Shau-Lin Shue

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