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Dive into the research topics where Hsiang-Huan Lee is active.

Publication


Featured researches published by Hsiang-Huan Lee.


international interconnect technology conference | 2015

A flexible top metal structure to improve ultra low-k reliability

K. F. Cheng; C. L. Teng; H. Y. Huang; Hsueh-Chung Chen; C.W. Shih; T. H. Liu; Cheng-Hsiung Tsai; C. W. Lu; Y.H. Wu; Hsiang-Huan Lee; Ming-Han Lee; M. H. Hsieh; B. L. Lin; Shang-Yun Hou; Chung-Ju Lee; Hsin-Hsien Lu; Tien-I Bao; Shau-Lin Shue; Chung-Yi Yu

High stresses generated from chip-package interactions (CPI), especially when large die is flip mounted on organic substrate using Pb-free C4 bumps, can easily cause low-k delamination. A novel scheme by applying an elastic material can effectively reduce the transmitted stresses and, thus, resolve the interfacial delamination issue. Along with an optimized chip-package integration solution, a reliable interconnect structure with good electrical performance, has been successfully demonstrated.


international interconnect technology conference | 2012

Uncured ELK as a chemical mechanical planarization stop layer in Cu/XLK interconnect

Y.H. Wu; Ming-Han Lee; Cheng-Hsiung Tsai; Hsiang-Huan Lee; Chung-Ju Lee; Hsin-Hsien Lu; Tien-I Bao; Shau-Lin Shue; Chung-Yi Yu

A novel approach of copper CMP stop layer using uncured extreme low-K was demonstrated to improve the within-wafer Rs uniformity on Cu/extra low-k (XLK) interconnect. This CMP stop layer could be converted into a low dielectric constant film by removing porogen with post CMP treatment, hence its impact on overalls film capacitance is minimized.


Archive | 2014

Method of semiconductor integrated circuit fabrication

Ching-Fu Yeh; Hsiang-Huan Lee; Chao-Hsien Peng; Hsien-Chang Wu


Archive | 2014

COPPER INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME

Chen-Hua Yu; Shau-Lin Shue; Hsiang-Huan Lee; Ching-Fu Yeh


Archive | 2010

Low resistance high reliability contact via and metal line structure for semiconductor device

Hsiang-Huan Lee; Ming Han Lee; Ming-Shih Yeh; Chen-Hua Yu; Shau-Lin Shue


Archive | 2015

Interconnect structure and manufacturing method thereof

Shin-Yi Yang; Hsi-Wen Tien; Ming-Han Lee; Hsiang-Huan Lee; Shau-Lin Shue


Archive | 2015

Method for via plating with seed layer

Shin-Yi Yang; Ching-Fu Yeh; Tz-Jun Kuo; Hsiang-Huan Lee; Ming Han Lee


Archive | 2013

Lithography Using High Selectivity Spacers for Pitch Reduction

Yu-Sheng Chang; Chung-Ju Lee; Cheng-Hsiung Tsai; Yung-Hsu Wu; Hsiang-Huan Lee; Hai-Ching Chen; Ming-Feng Shieh; Tien-I Bao; Ru-Gun Liu; Tsai-Sheng Gau; Shau-Lin Shue


Archive | 2013

METHOD OF FABRICATING COPPER DAMASCENE

Chao-Hsien Peng; Chi-Liang Kuo; Hsiang-Huan Lee; Shau-Lin Shue


Archive | 2015

Via pre-fill on back-end-of-the-line interconnect layer

Chao-Hsien Peng; Chi-Liang Kuo; Ming-Han Lee; Hsiang-Huan Lee; Shau-Lin Shue

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