Chieh-Fang Chen

High performance 0.1 /spl mu/m CMOS devices with 1.5 V power supply

This paper presents the design, fabrication, and characterization of high-performance 0.1 /spl mu/m-channel CMOS devices with dual n/sup +p/sup +/ polysilicon gates on 35 /spl Aring/-thick gate oxide. A 22 ps/stage CMOS-inverter delay is obtained at a power supply voltage of 1.5 V. The highest unity-current-gain frequencies (f/sub T/) measured are 118 GHz for nMOSFET, and 67 GHz for pMOSFET.<<ETX>>

A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BLs (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices [1] and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2M contacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.

Memory Architecture of 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding Method and Study of it's Program Inhibit Characteristics

The memory architecture of 3D vertical gate (3DVG) NAND Flash using plural island-gate SSL decoding method is discussed in detail. In order to provide a good array efficiency, 3DVG shares the wordlines (WL) in vertical direction, and BLs in lateral direction. In order to correctly decode the array, every channel BL has its own island-gate SSL device for the control. Meanwhile, many channel BLs are grouped together in one unit, and the staircase BL contacts are formed in order to decode various memory layers. Page operation is naturally defined by the selection of each island-gate SSL device. Due to the plural SSL devices, the 3DVG architecture inevitably has more pages when stacked layer number is increased, thus program inhibit stress is much larger than conventional 2D NAND. In this work, the program inhibit performances of 3DVG TFT NAND are discussed. Scaling capability down to 3Xnm node is also demonstrated.

Dynamic Resistance—A Metric for Variability Characterization of Phase-Change Memory

The resistance of phase-change-memory (PCM) cells measured during RESET programming (dynamic resistance, Rd) is found to be inversely proportional to the amplitude of the programming current, as Rd = [A/I] + B. We show that parameters A and B are related to the intrinsic properties of the memory cell, and demonstrate by means of experimental data that they could be used to characterize the cell-to-cell process-induced variability of PCM cells.

Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash

The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of 3D VG and its decoding method, we have developed several important design innovations to optimize this technology: (1) “Shift-BL scramble” to average the BL capacitances, providing uniform CBLs for various memory layers; (2) Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode; (3) Novel reverse read with “multi-Vt sensing technique” for different memory layers to compensate the Vt variation due to the layer-to-layer process difference; (4) Program inhibit method and technique to minimize the “Z-directional” self-boosting program disturb in 3D stackable memory. Optimized chip-level performances with excellent memory window for SLC and MLC operations are demonstrated on a 2-layer 3D VG NAND chip.

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 mu m CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 mu m CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited approximately=45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V.<<ETX>>

A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity

We demonstrate a novel vertical channel 3D NAND Flash architecture - SGVC. SGVC device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. Our novel array decoding method enables a tight-pitch (25nm HP) metal BL design to fulfill the large page size (16KB for one plane) for high-performance NAND product. The SGVC flat cell possesses excellent P/E window of ~10V, small X/Y/Z adjacent-cell interferences, good self-boosting inhibit, and >10K P/E cycling endurance. Due to the advantage of flat cell that is insensitive to etching CD, SGVC device is tolerant to the non-ideal vertical etching and has shown excellent device uniformity from layer to layer. In sharp contract to GAA VC, SGVC suffers no penalty from field-enhancement effect, thus has shown very robust read-disturb immunity against long-term gate stressing. Due to (1) two physical bits per X-Y cell footprint, and (2) efficient array design with minimal overhead, SGVC architecture has 2 to 4 times memory density than GAA VC 3D NAND at the same stacking layer number.

Influence of Bottom Contact Material on the Selective Chemical Vapor Deposition of Crystalline GeSbTe Alloys

Selective Chemical Vapor Deposition of Crystalline Ge-Sb-Te alloys initiating at the bottom metal contact of vias of various sizes has been accomplished. The method is based on selecting Sb and Te precursors which do not decompose on dielectric surfaces in the utilized temperature range.