Chien-Heng Wong
University of California, Los Angeles
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Publication
Featured researches published by Chien-Heng Wong.
IEEE Journal of Solid-state Circuits | 2017
Yuan Du; Wei-Han Cho; Po-Tsang Huang; Yilei Li; Chien-Heng Wong; Jieqiong Du; Yanghyo Kim; Boyu Hu; Li Du; Chun-Chen Liu; Sheau Jiung Lee; Mau-Chung Frank Chang
A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm2 in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4
international solid-state circuits conference | 2016
Wei-Han Cho; Yilei Li; Yuan Du; Chien-Heng Wong; Jieqiong Du; Po-Tsang Huang; Sheau Jiung Lee; Huan-Neng Ron Chen; Chewn-Pu Jou; Fu-Lung Hsueh; Mau-Chung Frank Chang
\mu \text{W}
symposium on vlsi circuits | 2016
Zuow-Zun Chen; Yilei Li; Yen-Cheng Kuan; Boyu Hu; Chien-Heng Wong; Mau-Chung Frank Chang
/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2018
Yilei Li; Kirti Dhwaj; Chien-Heng Wong; Yuan Du; Li Du; Yiwu Tang; Yiyu Shi; Tatsuo Itoh; Mau-Chung Frank Chang
The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past few years. Among those cutting-edge interface technologies, multi-band (multi-tone) signaling has shown great potential because of its high data-rate capability along with its low energy consumption [3]-[5]. With spectrally divided signaling, the multi-band transceiver can be designed to avoid spectral notches with extended communication bandwidth of multi-drop buses [4]. Also, its unique self-equalized double-sideband signaling renders the multi-band transceiver immune to inter-symbol interference caused by channel attenuation without additional equalization circuitry [5]. To further improve the capability and validate the scalability of multi-band signaling, we have realized a tri-band transceiver with four parallel lanes and achieved a total data rate of 40Gb/s, with total power consumption of 38mW in 28nm CMOS technology.
symposium on vlsi circuits | 2016
Yuan Du; Wei-Han Cho; Yilei Li; Chien-Heng Wong; Jieqiong Du; Po-Tsang Huang; Yanghyo Kim; Zuow-Zun Chen; Sheau Jiung Lee; Mau-Chung Frank Chang
A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from -88 to -109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from -16.8 to -34.6dBc, when operating at 2.4GHz.
IEEE Transactions on Circuits and Systems Ii-express Briefs | 2017
X. Shawn Wang; Xin Jin; Jieqiong Du; Yilei Li; Yuan Du; Chien-Heng Wong; Yen-Cheng Kuan; Chi-Hang Chan; Mau-Chung Frank Chang
In this paper, a fully synthesizable all-digital transmitter (ADTX) is first proposed. This transmitter (TX) uses Cartesian architecture and supports wide-band quadratic-amplitude modulation with wide carrier frequency range. Furthermore, the design methodology for ADTX and corresponding bandpass filter is discussed. This TX is synthesized with digital register transfer level-graphic database system flow, and can be easily implemented in any standard CMOS technology. An exemplary TX is synthesized by TSMC 28-nm standard cell library with extremely small area (0.0009 mm2) and supports carrier frequency as high as 6 GHz with excellent error vector magnitude (<−30 dB). To the best of the authors’ knowledge, this is the first work on a fully synthesizable design of RF transistors, allowing easy technology migration and portability.
IEEE Journal of Solid-state Circuits | 2017
Zuow-Zun Chen; Yen-Cheng Kuan; Yilei Li; Boyu Hu; Chien-Heng Wong; Mau-Chung Frank Chang
A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm2 in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4
design automation conference | 2016
Chun Chen Liu; Yen-Hsiang Wang; Yilei Li; Chien-Heng Wong; Tien Pei Chou; Young-Kai Chen; M.-C. Frank Chang
\mu \text{W}
radio frequency integrated circuits symposium | 2018
X. Shawn Wang; Chi-Hang Chan; Jieqiong Du; Chien-Heng Wong; Yilei Li; Yuan Du; Yen-Cheng Kuan; Boyu Hu; Mau-Chung Frank Chang
/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 μW/Gb/s/dB considering channel condition.
custom integrated circuits conference | 2018
Yiwu Tang; Chien-Heng Wong; Yuan Du; Li Du; Yilei Li; Mau-Chung Frank Chang
This brief presents a two-way time-interleaved two-step pipelined analog-to-digital converter (ADC) architecture built upon a new concept of virtual-ground sampling, featuring merged front-end track-and-hold, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the total-harmonic-distortion, bandwidth, and sampling rate (interleaving factor). A 2-GS/s 8b ADC using the new architecture was designed and fabricated in 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency.