Zuow-Zun Chen

14.9 Sub-sampling all-digital fractional-N frequency synthesizer with −111dBc/Hz in-band phase noise and an FOM of −242dB

The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLLs high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.

A wide-band 65nm CMOS 28–34 GHz synthesizer module enabling low power heterodyne spectrometers for planetary exploration

This paper presents a wide-band 28-34 GHz frequency synthesizer module developed to support THz spectrometer instruments for planetary exploration. The presented module features low power operation and a small form factor to be compatible with the demanding payload requirements of NASA planetary missions. The core of the module is a CMOS System-on-Chip (SoC) containing a sub-sampled phase-detector (SSPD) based phase lock-loop, power amplifier, power sensor and digital calibration. The demonstrated module draws a total of 81.2 mW of power from a USB connection and provides coverage from 28-34 GHz with output powers better than -4.0 dBm across the entire band. The offered mid-band phase noise is measured at -96.6 dBc/Hz evaluated at 1 MHz offset from the carrier.

CMOS (Sub)-mm-Wave System-on-Chip for exploration of deep space and outer planetary systems

This paper discusses the applicability of CMOS (sub)-mm-Wave System-on-Chips in space explorations of the solar system, especially planetary missions. Specifically assessed are issues related to high levels of radiation encountered in deep space. To exemplify the type of technology infusion that is possible, we specifically feature the incorporation of a previously developed “self-healing” 12/48 GHz CMOS frequency synthesizer into a current planetary sub-mm-wave (or Terahertz) heterodyne receiver instrument (PISSARRO) for the substantial benefit of payload size, area and weight reduction.

Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers

A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from -88 to -109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from -16.8 to -34.6dBc, when operating at 2.4GHz.

2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and −74dBc/Hz phase noise at 1MHz offset in 65nm CMOS

Spectra from 0.5 to 0.6THz play critical roles in planetary science, astrophysics and radio-astronomy as various chemical species including water, nitrates (NO2, N2O, NH3) and organics (CH4 and HCN) can either absorb or reflect radiation in this frequency regime. Accordingly, NASA and ESA have developed a wide range of spectroscopic sounding instruments to investigate our solar system. Current LO chains for spectroscopic receivers are implemented with discrete III-V devices and heavy waveguide assemblies. For instance, the 600GHz NASA PISSARRO spectrometer for Europa begins with a 33GHz PLL, tripled to 100GHz, doubled to 200GHz, and then tripled again to 600GHz via multiple waveguides. This LO chain occupies over 3000cm3, weighs 2.5kg, and consumes 11.5W of DC power.

A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS

A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm2 in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4

A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology

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DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers

/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 μW/Gb/s/dB considering channel condition.

6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices

This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.

28nm CMOSにおけるPAM16/256‐QAMとチャネル応答検出を可能にする転送クロックを用いた16Gb/s14.7mW3バンド認知シリアルリンク送信機【Powered by NICT】

In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. It demonstrates a phase noise reduction from −88 to −109 dBc/Hz at 1-MHz offset and an integrated phase noise reduction from −16.8 to −34.6 dBc when operating at 2.4 GHz.