King-Jien Chui

Lattice strain analysis of transistor structures with silicon–germanium and silicon–carbon source∕drain stressors

We report the characterization of strain components in transistor structures with silicon–germanium (Si0.75Ge0.25) and silicon–carbon (Si0.99C0.01) stressors grown by selective epitaxy in the source and drain regions. The spacing between the source and drain stressors is 35nm. Lattice strain analysis was performed using high-resolution transmission electron microscopy (HRTEM) and diffractograms obtained by fast Fourier transform of HRTEM images. The lateral strain component exx and the vertical strain component ezz were derived from the (220) and (002) reflections in the diffractogram, respectively. SiGe source and drain stressors lead to lateral compressive strain and vertical tensile strain in the Si channel. On the other hand, the SiC source and drain stressors give rise to lateral tensile strain and vertical compressive strain in the Si channel, an effect complementary to that of SiGe source∕drain stressors. The results of this work will be useful for channel strain engineering in complementary metal-...

n-MOSFET With Silicon–Carbon Source/Drain for Enhancement of Carrier Transport

A novel strained-silicon (Si) n-MOSFET with 50-nm gate length is reported. The strained n-MOSFET features silicon-carbon (Si_1-yC_y) source and drain (S/D) regions formed by a Si recess etch and a selective epitaxy of Si_1-yC_y in the S/D regions. The carbon mole fraction incorporated is 0.013. Lattice mismatch of ~0.56% between Si _0.987C_0.013 and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron-mobility enhancement. The conduction-band offset DeltaE_c between the Si_0.987C_0.013 source and the strained Si channel could also contribute to an increased electron injection velocity nu_inj from the source. Implementation of the Si_0.987C_0.013 S/D regions for n-MOSFET provides significant drive current I_Dsat enhancement of up to 50% at a gate length of 50 nm

Thin body silicon-on-insulator N-MOSFET with silicon-carbon source/drain regions for performance enhancement

We report a novel strained n-channel transistor structure featuring silicon-carbon (SiC) source and drain (S/D) regions formed on thin body SOI substrate. The SiC material is pseudomorphically grown by selective epitaxy and the carbon mole fraction incorporated is 1%. Lattice mismatch between SiC and Si results in uniaxial tensile strain in the Si channel region which contributes favorably to electron mobility enhancement. Drive current IDsat enhancement of 25% was observed for 90 nm gate length LG transistors, and IDsat enhancement of up to 35% was observed at LG of 70 nm. In addition, drive current enhancement shows dependence on device width and channel orientation. All transistors were formed on (001) SOI substrates. The largest IDsat enhancement is observed for transistors with the [010] channel orientation

Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon–Carbon Source/Drain Regions

We report the demonstration of a novel strained silicon-on-insulator N-MOSFET featuring silicon-carbon (Si1-yCy) source and drain (S/D) regions, tantalum nitride metal gate, and hafnium-aluminum oxide high-k gate dielectric. Due to the lattice mismatch between Si0.99C0.01 S/D stressors and Si, a lateral tensile strain is induced in the transistor channel, leading to substantial electron mobility enhancement. At a fixed OFF-state leakage of 100 nA/mum, the Sii-j/C1-yCy S/D N-MOSFET having a width of 4.7 mum achieves a drive current Josat enhancement of 16% over a control N-MOSFET. This iDsat enhancement, which is primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate length LG due to an increased strain level in the transistor channel as the Si1-yCy S/D stressors are placed in closer proximity. Slightly improved series resistance with Si1-yCy S/D regions in a strained N-MOSFET accounted for approximately 2% IDsat gain. In addition, a reduction of device width is found to reduce the drive current enhancement of the N-MOSFETs due to the presence of a transverse compressive strain in the transistor channel induced by the isolation regions.

Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFETs With Silicon–Carbon Source/Drain and Tensile-Stress Liner

We report the demonstration of 25-nm gate-length L_G strained nMOSFETs featuring the silicon-carbon source and drain (Si_1-yC_yS/D) regions and a thin-body thickness T _body of ~18 nm. This is also the smallest reported planar nMOSFET with the Si_1-yC_yS/D stressors. Strain-induced mobility enhancement due to the Si_1-yC_yS/D leads to a significant drive-current I_Dsat enhancement of 52% over the control transistor. Furthermore, the integration of tensile-stress SiN etch stop layer and Si_1-yC _yS/D extends the I_Dsat enhancement to 67%. The performance enhancement was achieved for the devices with similar subthreshold swing and drain-induced barrier lowering. The Si_1-yC_yS/D technology and its combination with the existing strained-silicon techniques are promising for the future high-performance CMOS applications

50 nm Silicon-On-Insulator N-MOSFET Featuring Multiple Stressors: Silicon-Carbon Source/Drain Regions and Tensile Stress Silicon Nitride Liner

A novel n-channel strained SOI transistor featuring silicon-carbon (SiC) source/drain (S/D) regions and tensile stress silicon nitride (SiN) liner is demonstrated for the first time. Drive current IDsat enhancement contributed by the dual stressors is found to be additive and a significant increase in IDsat of 55% is observed at a gate length LG of 50 nm. In addition, we report the dependence of drive current on channel orientation, with highest I Dsat observed for strained n-MOSFETs with the |010| channel direction. A study of the carrier transport characteristics indicate reduced channel back-scattering and enhanced carrier injection velocity due to the strain effects

Strained Thin-Body p-MOSFET With Condensed Silicon-Germanium Source/Drain for Enhanced Drive Current Performance

Strained p-MOSFETs with silicon-germanium (SiGe) source and drain (S/D) stressors were fabricated on thin-body silicon-on-insulator (SOI) substrate using a novel local oxidation or Ge condensation technique. By directly growing SiGe on the S/D regions and followed by a local Ge condensation process, the challenges imposed on Si recess etch on thin-body SOI substrates can be alleviated. In the Ge condensation step, the Ge content in the S/D regions may also be increased. At a gate overdrive of -1 V, strained p-MOSFETs show an enhancement in the saturation drive current Ion of up to 38% over the control p-MOSFETs. This significant Ion enhancement is attributed to strain-induced band structure modification, which reduces the hole effective mass along the transport direction. The improved series resistance of the strained devices with SiGe S/D accounted for approximately one-third of the Ion enhancement.

Strained-SOI n-Channel Transistor With Silicon–Carbon Source/Drain Regions for Carrier Transport Enhancement

A novel 80 nm gate length strained-Si n-channel transistor structure with lattice-mismatched source and drain (S/D) formed on thin-body silicon-on-insulator substrate is reported. The strained transistor features silicon-carbon (Si1-yCy) S/D regions, which are pseudomorphically grown by selective epitaxy. The incorporated carbon mole fraction y is 0.01. The lattice mismatch between Si0.99C0.01 and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The implementation of the Si0.99C0.01 stressors provides a substantial drive current IDsat enhancement of 11% over a control transistor at a gate length of 80 nm and a width of ~1.1 mum, while the enhancement for the linear drive current IDlin is approximately two times larger. Pulse measurements were also performed to correct for self-heating effects

Sub-30 nm Strained p-Channel Fin-Type Field-Effect Transistors with Condensed SiGe Source/Drain Stressors

Strained p-channel fin-type field-effect transistors (FinFETs) with SiGe source and drain (S/D) regions formed by a Ge condensation process is demonstrated. SiGe epitaxial layer was grown on the sidewalls at the S/D regions after a successful removal of both the polysilicon gate and nitride spacer stringer. Condensation of the SiGe at the S/D region was subsequently performed. The novel local Ge condensation not only drives Ge into the Si fin and/or increases the Ge concentration in the S/D regions for enhanced strain effects, but also eliminates the need for S/D recess etch, leading to process simplicity. Compared to a FinFET with uncondensed Si1-xGex S/D, FinFETs with condensed Si1-yGey S/D exhibit 28% higher drive current. Devices with gate lengths down to 26 nm were demonstrated with excellent control of short-channel effects.

Carrier Backscattering Characteristics of Strained N-MOSFET Featuring Silicon-Carbon Source/Drain Regions

The physics of carrier transport in a sub-90nm strained SOI n-MOSFET with silicon-carbon (SiC) source/drain (S/D) regions is investigated for the first time. Significant improvement in carrier backscattering coefficient rsat and source injection velocity vinj accounts for the large drive current IDsat enhancement in SiC S/D transistors. The improvement in rsat, is attributed to the modulation of conduction band barrier which results in a shorter critical length for carrier backscattering. On the other hand, strain-induced conduction band valley splitting leads to a reduced electron effective mass and thus contributes to the vinj enhancement. In addition, we evaluate the dependence of drive current performance on carrier injection velocity and ballistic efficiency in a short channel MOSFET