Chih-He Lin

Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM

A novel HfO2-based resistive memory with the TiN electrodes is proposed and fully integrated with 0.18 mum CMOS technology. By using a thin Ti layer as the reactive buffer layer into the anodic side of capacitor-like memory cell, excellent memory performances, such as low operation current (down to 25 muA), high on/off resistance ratio (above 1,000), fast switching speed (5 ns), satisfactory switching endurance (>106 cycles), and reliable data retention (10 years extrapolation at 200degC) have been demonstrated in our memory device. Moreover, the benefits of high yield, robust memory performance at high temperature (200degC), excellent scalability, and multi-level operation promise its application in the next generation nonvolatile memory.

Evidence and solution of over-RESET problem for HfO X based resistive memory with sub-ns switching speed and high endurance

The memory performances of the HfOX based bipolar resistive memory, including switching speed and memory reliability, are greatly improved in this work. Record high switching speed down to 300 ps is achieved. The cycling test shed a clear light on the wearing behavior of resistance states, and the correlation between over-RESET phenomenon and the worn low resistance state in the devices is discussed. The modified bottom electrode is proposed for the memory device to maintain the memory window and to endure resistive switching up to 1010 cycles.

A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications

This work demonstrates the first fabricated macro-level RRAM-based nonvolatile SRAM (nvSRAM) that use a new 8T2R (Rnv8T) cell to achieve fast NVM storage and low VDDmin read/write operations. The Rnv8T cell uses two fast-write low-current RRAM devices, 3D stacked over the 8T, to achieve low store energy with a compact cell area (1.6x that of a 6T cell). A 2T RRAM-switch provides both RRAM control and write-assist functions. This write assist feature enables Rnv8T cell to use read favored transistor sizing against read/write failure at a lower VDD. The fabricated 16Kb Rnv8T macro achieves the lowest store energy and R/W VDDmin (0.45V) than other nvSRAM and “SRAM+NVM” solutions.

Challenges and opportunities for HfO X based resistive random access memory

The binary oxide based resistive memories showing superior electrical performances on the resistive switching are reviewed in this paper. The status and challenges of the HfOX based resistive device with excellent memory properties are presented. Several future challenges for the filamentary type switching device are also addressed.

RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme

The Resistive Random Access Memory (RRAM) is a new type of non-volatile memory based on the resistive memory device. Researchers are currently moving from resistive device development to memory circuit design and implementation, hoping to fabricate memory chips that can be deployed in the market in the near future. However, so far the low manufacturing yield is still a major issue. In this paper, we propose defect and fault models specific to RRAM, i.e., the Over-Forming (OF) defect and the Read-One-Disturb (R1D) fault. We then propose a March algorithm to cover these defects and faults in addition to the conventional RAM faults, which is called March C*. We also develop a novel squeeze-search scheme to identify the OF defect, which leads to the Stuck-At Fault (SAF). The proposed test algorithm is applied to a first-cut 4-Mb HfO2-based RRAM test chip. Results show that OF defects and R1D faults do exist in the RRAM chip. We also identify specific failure patterns from the test results, which are shown to be induced by multiple short defects between bit-lines. By identifying the defects and faults, designers and process engineers can improve the RRAM yield in a more cost-effective way.

A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application

This study demonstrates a new 7T2R nonvolatile SRAM (nvSRAM) with 3D ReRAM stacked structure for normally-off computing application. With this structure, the fully performance of SRAM can work well in active mode, and reduce the leakage current in power-off mode. High performance HfOx based ReRAM is used for high speed storage element and exhibits an instant-on characteristic. The present 7T2R nvSRAM cell includes a 1T2R RRAM (1 transistor/2 resistive memory) cell and a 6T SRAM circuit, which is low area penalty and achieve the nvSRAM function. The write margin is improved over 1.03x and 1.37x larger than that of 6T SRAM and 6T2R nvSRAM. The access time and read/write power consumption in 7T2R nvSRAM is better than that of 8T2R structure. Finally, a 16 Kb macro was fabricated with a 0.18 μm TSMC FEOL and ITRI BEOL. According to the measurement result, the VDDmin can be low down to 0.7 V and access time can be fast as 8.3 ns without pad delay. The data storage time is only 10 ns for SET and RESET in the ReRAM cell.

Training-based forming process for RRAM yield improvement

Over the past decade, the resistive memory device known as RRAM has been studied extensively in many ways, and many of its problems have been identified, discussed, and some solved. It is time to move from material, process, and device to circuit design and yield, in order to commercialize RRAM. However, as we move from resistive device to memory circuit, new problems do appear, partly because the operating conditions of resistive devices on real RRAM circuit differ from those in an experimental environment for single devices. In this paper, an over forming problem has been identified from our analysis, and we propose a solution based on training sequence. As a result, by solving the over forming problem, RRAM yield can be improved significantly. RRAM; forming process; training sequence; yield improvement; non-volatile memory; memory testing

Low current and voltage resistive switching memory device using novel Cu/Ta 2 O 5 /W structure

Low current/voltage (∼10 nA/1.0V) resistive switching memory device in a Cu/Ta<inf>2</inf>O<inf>5</inf>/W structure has been proposed. The low resistance state (R<inf>Low</inf>) of the memory device decreases with increasing the programming current from 10 nA to 1mA, which can be useful for multi-level of data storage. This resistive memory devices have stable threshold voltage, good resistance ratio (R<inf>High</inf>/R<inf>Low</inf>) of 5.3×10⁷, good endurance of ≫10³ cycles, and excellent retention (≫11 hours) with resistance ratio of ≫ 9×10³ can be useful in future non-volatile memory applications.

Low current bipolar resistive switching memory using Cu metallic filament in Ge 0.2 Se 0.8 solid-electrolyte

Low current/voltage (1 nA/1.3V) operation of resistive switching memory device using Cu metallic filament in Ge<inf>0.2</inf>Se<inf>0.8</inf> solid-electrolyte has been investigated. This resistive memory device have a large resistance ratio of > 10 at 1 nA current compliance, good endurance of ~10⁵ cycles, and good data retention with a current of 1 nA up to 2×10³ seconds. The low resistance state decreases with increasing the programming current from 1 nA to 500 µA, which can be useful for future nanoscale MLC applications. A strong Cu metallic filament is investigated by monitoring the negative erase current (I<inf>e</inf>).