Chih-Hsuan Tai

A novel high-performance junctionless vertical MOSFET produced on bulk-Si wafer

In this paper, we propose a junctionless vertical MOSFET (JLVMOS) based on bulk-Si wafer. According to the numerical simulations, the proposed JLVMOS can get a steep subthreshold swing (S. Swing), reduced DIBL, and higher ION/IOFF ratio, in comparison to a junctionless planar SOI MOSFET. This is because the vertical double-gate (DG) structure truly helps reduce the short-channel effects (SCEs). More importantly, SOI wafer is not necessary as a starting material for our proposed junctionless transistor, which is good for low-cost mass production.

Numerical study of performance comparison between junction and junctionless thin-film transistors

This paper for the first time presents a performance comparison between junction and junctionless thin-film transistors (TFTs) by using TCAD simulations. Note that the DIBL and S.S. of a junctionless TFT (JLTFT) are larger and higher, respectively, than those of its junction TFT (JTFT) counterpart. Although the JLTFT gets a higher current drive based on the same Vov as compared with the JTFT, its short-channel characteristics are worse and degraded. These results can be attributed to the fact that the major carriers in channel region for a JTFT make itself a barrier to carrier scattering, whereas, the JTFT does not have this problem, leading to get a high current drive. On the other hand, it may be owing to the grain boundary effects for a JLTFT to degrade its short-channel behavior. Fortunately, these results are still acceptable for scaled dimensions of TFTs.

A 3-D simulation study of a novel vertical MOSFET with source-tied (STVMOS)

In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 ION/IOFF current ratio.

A novel vertical MOSFET with bMPI structure for 1T-DRAM application

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

Characterization of a body-tied vertical MOSFET

In this paper, a non-classical body-tied vertical field-effect transistor (BTVFET) utilizing the self-aligned technique is presented and demonstrated. Based on the simulations, we find out that the electrical characteristics of the BTVFET are better than that of the conventional SOI VFET, including the outstanding ability of heat dissipation, higher channel mobility, lower parasitic capacitance, and reduced gate leakage current. The excellent subthreshold swing (~77 mV/dec) of the BTVFET is also attractive. In addition, the shallow junction is easy to form because the partially insulating oxide is under the drain regions in our proposed quasi-SOI vertical MOSFET. Hence, it is believed that the BTVFET can become one of the candidates for future CMOS scaling.

Thermal characteristics of an advanced bMPI-based 1T-DRAM cell

In this paper, we study the thermal characteristics of the bMPI-based 1T-DRAM cell. For a bMPI-FET, it can not only improve the thermal stability about 38% compared with the bPDSOI-FET due to the S/D-tied scheme, but also maintain the desired short-channel characteristics due to the block oxide structure.

Study of junctionless pseudo tri-gate vertical MOSFETs for RF/analog applications

In this study, junctionless technology employed for fabricating pseudo tri-gate vertical (PTGV) MOSFETs is proposed and the RF/analog performance is also investigated and demonstrated. According to simulation results, the excellent performances such as high transconductance (gm), high cut-off frequency (ƒT), and high transconductance generation factor (gm/Id) are achieved. The numerical results also provide a prediction of an 8nm gate length PTGV and JPTGV for RF applications.

A qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs

In this work, a qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs is carefully investigated. According to numerical simulations, we find out that both gm and gD of junction poly-Si TFT are higher than the junctionless poly-Si TFT at a fixed IDS. Based on the same S/D doping concentration the junctionless poly-Si TFT can have a better short-channel behavior than its counterpart. Thus, it can be proved that a junctionless poly-Si TFT is a good option for AMLCD and AMOLED Applications.

Electrical Characterization of 10-nm π-Shaped S/D MOSFETs

In this paper, we numerically explore electrical characteristics of a simple device called the π-shaped source/drain (π-S/D) MOS transistor. Some techniques such as Si/SiGe epitaxial growth and selective SiGe etch process are implemented for the fabrication of quasi-SOI devices with an S/D tie. More importantly, a new method presented here for fabricating π-S/D MOSFETs does not require any additional mask step due to self-alignment process being exploited. The isolation technique is carried out only after S/D annealing, resulting in only four extra process steps introduced in this new quasi-SOI technology. According to numerical simulations, the new π-S/D structure has better control on the short-channel and thermal effects compared with the conventional (conv.) π-S/D structure. Despite Miller capacitance sacrifice behaviour owing to the absence of the conv. isolation approach before gate definition, which causes an increase in the body area under the gate, NMOSFET intrinsic delay τ and cutoff frequency f T are within acceptable limits for this new structure.

RF/Analog Performance of Novel Junctionless Vertical MOSFETs

In this paper, we analyze the radio frequency (RF) performance for novel junctionless vertical MOSFETs (JLVMOS) with different thicknesses of silicon pillar (T Si = 5, 10 nm). In addition, a junctionless planar SOI MOSFET is also designed for the comparison in this work. According to the numerical simulations, the JLVMOS of T Si = 5 nm gets the highest in g m and g m/I DS, but the T Si = 10 nm one gets the highest in A VI. Moreover, due to the double-gate (DG) structure of the VMOS, it can increase the gate controllability over the channel region.