Yi-Hsuan Fan

Numerical Study of a Highly Scaled Bulk MOSFET With Block Oxide and Source/Drain-Tied Structure

In this paper, we present a highly scaled bulk metal-oxide-semiconductor field-effect transistor with block oxide (BO) and source/drain (S/D)-tied structure that meets the International Technology Roadmap for Semiconductors requirements for high-performance devices. This new device requires only a simple BO fabrication process using SiGe-Si epitaxial growth with selective SiGe removal and requires no additional lithography masks. This proposed BO fabrication process is simple due to it being controllable, repeatable, and fully compatible with standard complementary metal-oxide-semiconductor technology. According to 3-D simulations, our proposed structure not only exhibits its structural advantages to overcome scaling obstacles but also extends the use of planar bulk technology to the decananometer regime.

Numerical study of performance comparison between junction and junctionless thin-film transistors

This paper for the first time presents a performance comparison between junction and junctionless thin-film transistors (TFTs) by using TCAD simulations. Note that the DIBL and S.S. of a junctionless TFT (JLTFT) are larger and higher, respectively, than those of its junction TFT (JTFT) counterpart. Although the JLTFT gets a higher current drive based on the same Vov as compared with the JTFT, its short-channel characteristics are worse and degraded. These results can be attributed to the fact that the major carriers in channel region for a JTFT make itself a barrier to carrier scattering, whereas, the JTFT does not have this problem, leading to get a high current drive. On the other hand, it may be owing to the grain boundary effects for a JLTFT to degrade its short-channel behavior. Fortunately, these results are still acceptable for scaled dimensions of TFTs.

A 3-D simulation study of a novel vertical MOSFET with source-tied (STVMOS)

In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 ION/IOFF current ratio.

A novel vertical MOSFET with bMPI structure for 1T-DRAM application

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

Additional-Body Effects in a Self-Aligned Deca-Nanometer Ultrathin-Body and Buried Oxide Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor: A Three-Dimensional Simulation Study

In this paper, we numerically investigate the additional-body effects (ABEs) created by the isolation-last fabrication process of a self-aligned deca-nanometer ultrathin-body and buried oxide (UTBB) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET). The reasons for the devices new electrical characteristics are also explained in detail. The additional silicon body volumes of the UTBB SOI MOSFET are found to improve the subthreshold swing and the on/off current ratio. The additional body has a negative effect, however, upon both the gate leakage current and the total gate capacitance, when compared with a standard UTBB SOI MOSFET.

A Three-Dimensional Simulation Study of Source/Drain-Tied Double-Gate Fin Field-Effect Transistor Design for 16-nm Half-Pitch Technology Generation and Beyond

This paper presents a three-dimensional (3D) simulation study of source/drain (S/D)-tied (SDT) double-gate (DG) fin field-effect transistor (FinFET) design for 16-nm half-pitch technology generation and beyond using technology computer-aided design (TCAD) tools. A simple process to fabricate the proposed SDT FinFET is proposed. An investigation of the fin width (Wfin) on the electrical characteristics is shown, suggesting that a reduced Wfin is good for both the suppression of short-channel effects and the reduction of parasitic capacitance in SDT FinFETs. Also, the self-heating can be well controlled in our proposed SDT FinFET which is a difficult task for SOI family. The proposed FinFET is also compared with the existing experimental data, showing that the SDT FinFET not only demonstrates desired short-channel characteristics due to its inherent structure advantages (partially insulating oxide under the channel region), but also reduces the costs of device fabrication due to its simple process method and planar-like structure.

Characterization of a body-tied vertical MOSFET

In this paper, a non-classical body-tied vertical field-effect transistor (BTVFET) utilizing the self-aligned technique is presented and demonstrated. Based on the simulations, we find out that the electrical characteristics of the BTVFET are better than that of the conventional SOI VFET, including the outstanding ability of heat dissipation, higher channel mobility, lower parasitic capacitance, and reduced gate leakage current. The excellent subthreshold swing (~77 mV/dec) of the BTVFET is also attractive. In addition, the shallow junction is easy to form because the partially insulating oxide is under the drain regions in our proposed quasi-SOI vertical MOSFET. Hence, it is believed that the BTVFET can become one of the candidates for future CMOS scaling.

Thermal characteristics of an advanced bMPI-based 1T-DRAM cell

In this paper, we study the thermal characteristics of the bMPI-based 1T-DRAM cell. For a bMPI-FET, it can not only improve the thermal stability about 38% compared with the bPDSOI-FET due to the S/D-tied scheme, but also maintain the desired short-channel characteristics due to the block oxide structure.

Study of junctionless pseudo tri-gate vertical MOSFETs for RF/analog applications

In this study, junctionless technology employed for fabricating pseudo tri-gate vertical (PTGV) MOSFETs is proposed and the RF/analog performance is also investigated and demonstrated. According to simulation results, the excellent performances such as high transconductance (gm), high cut-off frequency (ƒT), and high transconductance generation factor (gm/Id) are achieved. The numerical results also provide a prediction of an 8nm gate length PTGV and JPTGV for RF applications.

DC characteristics of high performance self-aligned bulk-Si dual-channel source/drain-tied MOSFETs

We present a novel bulk-Si dual-channel source/drain-tied (DCSDT) MOSFET with the multiple epitaxial growth of SiGe/Si layers, and selective SiGe removal to form the block oxide island (BOI). Based on the simulations, the SDT scheme achieves better DC characteristics than body-tied (BT) scheme such as: Ion (20% increased), Ioff (71% reduced), Rsd (5.3% decreased), S.S. (19% improved), DIBL (35% reduced), τ (15.5% reduced), 1/τ (17.1% increased), and significantly improved thermal stability. Furthermore, the designed process is totally self-aligned, which is a promising candidate for future device scaled down.