Yu-Che Chang

A 3-D simulation study of a novel vertical MOSFET with source-tied (STVMOS)

In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 ION/IOFF current ratio.

A novel vertical MOSFET with bMPI structure for 1T-DRAM application

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

Characterization of a body-tied vertical MOSFET

In this paper, a non-classical body-tied vertical field-effect transistor (BTVFET) utilizing the self-aligned technique is presented and demonstrated. Based on the simulations, we find out that the electrical characteristics of the BTVFET are better than that of the conventional SOI VFET, including the outstanding ability of heat dissipation, higher channel mobility, lower parasitic capacitance, and reduced gate leakage current. The excellent subthreshold swing (~77 mV/dec) of the BTVFET is also attractive. In addition, the shallow junction is easy to form because the partially insulating oxide is under the drain regions in our proposed quasi-SOI vertical MOSFET. Hence, it is believed that the BTVFET can become one of the candidates for future CMOS scaling.

Thermal characteristics of an advanced bMPI-based 1T-DRAM cell

In this paper, we study the thermal characteristics of the bMPI-based 1T-DRAM cell. For a bMPI-FET, it can not only improve the thermal stability about 38% compared with the bPDSOI-FET due to the S/D-tied scheme, but also maintain the desired short-channel characteristics due to the block oxide structure.

Study of junctionless pseudo tri-gate vertical MOSFETs for RF/analog applications

In this study, junctionless technology employed for fabricating pseudo tri-gate vertical (PTGV) MOSFETs is proposed and the RF/analog performance is also investigated and demonstrated. According to simulation results, the excellent performances such as high transconductance (gm), high cut-off frequency (ƒT), and high transconductance generation factor (gm/Id) are achieved. The numerical results also provide a prediction of an 8nm gate length PTGV and JPTGV for RF applications.

A novel planar-type body-connected FinFET device fabricated by self-align isolation-last process

A new planar-type body-connected FinFET structure produced by the isolation-last self-align process is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. The new process step first defines the gate region and then the active region, thus it can achieve fully self-alignment undoubtedly. Besides, due to the isolation-last process (ILP), an additional body region (ABR) is exhibited under the gate region thereby improving the device electrical characteristics and the subthreshold properties. Its DIBL and subthreshold swing becomes better compared with its counterpart because the lower source/drain resistance and the wider device effective-width can be obtained. For the same reason, this new device shows a higher transconductance (GM) behavior. And its drain conductance (GD) also maintains a good electrical performance with no kink effect compared with the planar-type single top-gate FinFET. With ABR under the gate layer, the lattice temperature is decreased and the thermal instability is alleviated compared with its counterpart.

RF performance of the novel planar-type body-connected FinFET fabricated by isolation-last and self-alignment process

In this paper, we for the first time demonstrate a detailed radio frequency (RF) simulation study of the novel planar-type body-connected FinFET with 45 nm gate length, for which the DC behavior exhibits better I<inf>ON</inf>-I<inf>OFF</inf> current ratio and improved transconductance performance when compared with a planar-type FinFET. The RF characteristics are carried out as functions of gate voltage (V<inf>G</inf>) and drain current (I<inf>D</inf>) as well as the overdrive voltage (V<inf>OV</inf>). In addition, the total gate capacitance (C<inf>gg</inf>) is also reported.

A qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs

In this work, a qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs is carefully investigated. According to numerical simulations, we find out that both gm and gD of junction poly-Si TFT are higher than the junctionless poly-Si TFT at a fixed IDS. Based on the same S/D doping concentration the junctionless poly-Si TFT can have a better short-channel behavior than its counterpart. Thus, it can be proved that a junctionless poly-Si TFT is a good option for AMLCD and AMOLED Applications.

Electrical Characterization of 10-nm π-Shaped S/D MOSFETs

In this paper, we numerically explore electrical characteristics of a simple device called the π-shaped source/drain (π-S/D) MOS transistor. Some techniques such as Si/SiGe epitaxial growth and selective SiGe etch process are implemented for the fabrication of quasi-SOI devices with an S/D tie. More importantly, a new method presented here for fabricating π-S/D MOSFETs does not require any additional mask step due to self-alignment process being exploited. The isolation technique is carried out only after S/D annealing, resulting in only four extra process steps introduced in this new quasi-SOI technology. According to numerical simulations, the new π-S/D structure has better control on the short-channel and thermal effects compared with the conventional (conv.) π-S/D structure. Despite Miller capacitance sacrifice behaviour owing to the absence of the conv. isolation approach before gate definition, which causes an increase in the body area under the gate, NMOSFET intrinsic delay τ and cutoff frequency f T are within acceptable limits for this new structure.

A highly scalable Π-shaped source/drain quasi-SOI MOS transistor

This paper presents a highly scalable Π-shaped source/drain (Π-S/D) quasi-silicon-on-insulator (SOI) MOSFET and summarizes its preliminary characteristics compared with the recessed S/D SOI MOSFET and international technology roadmap for semiconductors (ITRS) roadmap values. SiGe-Si epitaxial growth, Si and SiGe etching, growth of epitaxial Si, and selective SiGe removal are used to form the Π-S/D in the quasi-SOI fabrication that no additional lithography mask is needed due mainly to the isolation-last-formed structures. Hence the advantages of the proposed quasi-SOI over conventional one, in device fabrication, are that the new quasi-SOI process can not only be completely compatible with the standard CMOS process, but can also achieve single-crystal silicon S/D regions. The three-dimensional numerical simulations carried out prove that a modified Π-S/D quasi-SOI transistor can meet ITRS requirements for high-performance devices in the 20 nm technology node and it means that the potential for planar bulk technology can still be used continuously.