Kuo-Ching Huang

The anomalous behavior of hydrogenated/unhydrogenated polysilicon thin-film transistors under electric stress

The characteristics of high-temperature processed thin-film transistors (TFTs) with/without plasma hydrogenation under the stress condition of V/sub ds/=-15 V and V/sub gs/=0 V have been investigated and compared. It is found that, after stress, the subthreshold swing is greatly improved for unhydrogenated TFTs but not for hydrogenated TFTs. Also, the off-state current is deteriorated for unhydrogenated TFTs but, on the contrary, it is improved for hydrogenated TFTs. A model that takes the effect of hydrogen passivation into account is proposed to interpret the anomalous behavior of TFTs under electric stress.

Mechanism of device instability for unhydrogenated polysilicon TFTs under off-state stress

The effects of off-state stress (Vgs = 0 V, Vds = 0 to -20 V) on unhydrogenated p-channel polysilicon thin-film transistors (TFTs) were studied. It was observed that the post-stressed subthreshold swing is first improved due to the annealing effect from the interaction of tunnelling electrons and captured holes. As the stress time increases or as the stress bias increases, the generation of traps caused by tunnelling electrons will cancel out the annealing effect and then degrade the subthreshold swing. In addition, the trapping of tunnelling electrons in the gate oxide causes a shift of threshold voltage. However, improving the quality of the gate oxide interface by oxidation of the channel polysilicon on submicrometre bottom-gate TFTs can reduce the impact of the off-state stress.

Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

The effects of the substrate bias on the characteristics of split-gate EEPROM/Flash memory cells have been investigated. It is experimentally demonstrated that applying negative substrate bias (NSB) can improve the programming and erasing speed significantly. The improvements can be attributed that NSB effectively increase the needed electrical fields for fast programming and erasing, respectively. Furthermore, the cycling endurance is improved considerably if NSB is applied for programming and erasing operation both.

Influence of source coupling on the programming and degradation mechanisms of split-gate flash memory devices

In this paper, the mechanism of programming operation considering the source-to-floating gate coupling ratio (SCR) in split-gate source-side injected flash memory has been discussed and experimentally demonstrated. The effects of SCR on the programming performance and cycling endurance have also been investigated in detail. The experimental results indicate that the cell with higher SCR possesses a higher programming speed. Under the same programming speed, the higher-SCR cell shows larger cycling endurance compared to lower-SCR cell.

Effects of different tungsten polycide process on the effective channel length and performance of deep submicron CMOS transistors

The effects of different tungsten polycide technologies on the effective channel length and electrical performance of scaled CMOS transistors fabricated by rapid thermal annealing (RTA) have been investigated. Contrary to previous studies, it is found that the sputtered WSi/sub x/ device produces a larger reduction in channel length, a result which is confirmed by gate-to-drain overlap capacitance C/sub GD/ measurement. Experiments also indicate that the sputtered WSi/sub x/ devices possess a lower driving ability, and have higher off state leakage not only for the short channel but also for the long channel range.

A novel programming technique for highly scalable and disturbance immune flash EEPROM

Abstract The program speed of a selected cell and the program disturbance of unselected cells sharing the common program-line in split-gate source-side injected flash memory has been investigated. It is found that the program disturbance becomes severe as the control gate length decreases. In this letter, we first propose a novel program technique by applying a negative bias to inhibited word-line to improve the trade-off between program speed and program disturbance. The experimental results indicate that the new program technique is a good candidate for future high-density, high-disturbance-immunity flash EEPROM memory applications.

High performance submicron bottom gate TFTs with self aligned Ti-silicide interpoly contact and poly-channel oxidation for high-density SRAM

Abstract A self-aligned Ti-silicide interpoly contact for submicron bottom-gate TFT-SRAM with poly-channel oxidation is presented. In this new scheme, oxidation of poly-channel improves subthreshold swing and leakage current of TFTs, but degrades cell stability because of voltage drop across interpoly contact. Using a-Si/Ti bilayer process on backside oxide of poly-channel after channel oxidation and interpoly contact definition, self-aligned Ti-silicide interpoly contact can be formed and voltage drop across the interpoly contact can be greatly reduced. As a result, low subthreshold swing and high on/off ratio for unhydrogenated TFT in series with interpoly contact has been realized.

EFFECTS OF TUNGSTEN POLYCIDE PROCESS AND POST-POLYOXIDATION RAPID THERMAL PROCESS ON ELECTRICAL CHARACTERISTICS OF THIN POLYSILICON OXIDE

The effects of the tungsten polycide technologies and rapid thermal annealing (RTA) on thin polyoxide electrical characteristics have been investigated. It is found that a thin polyoxide with dichlorosilane (DCS)-based chemical vapor deposition (CVD) WSiX exhibits both good J-E characteristics and reliability. This is due to moderated fluorine incorporation, which improves poly-Si/SiO2 interfaces region but not degrades the bulk polyoxide. Moreover, the post-polyoxidation RTA is also found to improve the polyoxide quality. According to the results, the DCS-based CVD WSiX with post-polyoxidation RTA is a good candidate for polycide gate technique in high-density nonvolatile memories.